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ADM7008 octal ethernet 10/100m phy datasheet versi o n 1.0 admtek . com.tw inform atio n in th is do cu m e n t is p r ov id ed in con n ect i o n wi t h adm t e k pr o duct s . adm t e k m a y m a ke chan ges t o s p e c i f i cat i ons a n d pr o duct desc ri pt i o n s at an y time, with ou t n o tice. design ers m u st n o t rely o n the absence or characteristics of any feat u r es o r i n st ruct i o ns m a rked ?re s er ved? o r ? u nde f i ned?. a d m t e k reserv es t h ese for fu t u re d e finitio n and sh all h a v e no resp onsib ility wh atsoev er fo r con f li cts o r in co m p atib ilit i e s arising fro m fu tu re ch ang e s to th em the pr o duct s m a y cont ai n de si gn de fect s or err o rs k n o w as errat a , w h i c h m a y cause t h e pr o duct t o devi at e from publis hed specifications. curre n t cha r a c terized erra ta are av ailab l e on requ est. to ob tain latest doc um ent a t i on pl ease c o nt act y ou l o cal a d m t e k sal e s of fi ce o r vi si t ad m t ek?s we bsi t e at h ttp ://www.admtek . co m . tw ? copyright 2003 by admtek incorporat ed all rights reserved *t hi rd - p art y b r an ds a n d nam e s are t h e pr o p e rt y of t h ei r res p ect i v e ow ne rs .
admtek inc. v1.0 about this manual intended audience structure this data sheet contains 6 chapters chapter 1 product overview chapter 2 interface descrip tion chapter 3 function description chapter 4. register description chapter 5. electrical specification chapter 6. packaging revision history d a t e v e r s i o n c h a n g e 2 3 jan u a r y 2003 1.0 first release of ADM7008 customer support admtek incorporated, 2f, no.2, li-hsin rd., science-based industrial park, hsinchu, 300, taiwan, r.o.c. sales information tel + 886-3-5788879 ADM7008 fax + 886-3-5788871
admtek inc. v1.0 table of contents chapter 1 product overview ........................................................................................ 1-1 1 . 1 overview .......................................................................................................... 1-1 1 . 2 f e a t u r e s ............................................................................................................ 1 - 2 1 . 3 b l o c k diagram ................................................................................................. 1 - 3 1 . 4 abbreviations ................................................................................................... 1-3 1 . 5 c o n v e n t i o n s ..................................................................................................... 1 - 5 1.5.1 data lengths ............................................................................................ 1-5 1.5.2 register type descriptions ...................................................................... 1-5 1.5.3 pin type descriptions .............................................................................. 1-5 chapter 2 interface description ................................................................................... 2-1 2 . 1 pin diagram ..................................................................................................... 2-1 2 . 2 p i n d e s c r i p t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.1 twisted pair interface, 32 pins ................................................................ 2-2 2.2.2 ground and power, 20 pins ..................................................................... 2-2 2.2.3 mode setting ............................................................................................ 2-2 2.2.4 clock input select .................................................................................... 2-2 2.2.5 clock input, 3 pins ................................................................................... 2-3 2.2.6 rmii/s m ii interface, 48 pins ................................................................... 2-3 2.2.7 atpg signals, 2 pins ............................................................................. 2-16 2.2.8 reset pin ................................................................................................ 2-16 2.2.9 control signals, 3 pins ........................................................................... 2-16 2.2.10 led interface, 2 pins ............................................................................. 2-17 2.2.11 regulator c ontrol, 2 pins ...................................................................... 2-17 2.2.12 digital pow e r / g r o u n d , 1 3 p i n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 chapter 3 function description ................................................................................... 3-1 3 . 1 10/100m phy block ....................................................................................... 3-2 3.1.1 100base-x module ................................................................................... 3-2 3.1.2 100base-tx receiver ............................................................................... 3-2 3.1.3 100base-tx transmitter .......................................................................... 3-7 3.1.4 1 0 0 b a s e - f x r e c e i v e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.1.5 100base-fx transmitter .......................................................................... 3-8 3.1.6 10base-t module ..................................................................................... 3-8 3.1.7 operation modes ..................................................................................... 3-8 3.1.8 manchester encoder/decoder ................................................................. 3-8 3.1.9 transmit driver and receiver ................................................................. 3-9 3.1.10 smart squelch .......................................................................................... 3-9 3.1.11 carrier sense ........................................................................................... 3-9 3.1.12 collision detection ................................................................................ 3-10 3.1.13 jabber function ..................................................................................... 3-10 3.1.14 link test function ................................................................................. 3-10 3.1.15 automatic l i nk polarity detection ........................................................ 3-11 3.1.16 clock synthesizer ................................................................................... 3-11 3.1.17 cable broken auto detection ................................................................ 3-11 3.1.18 auto negotiation .................................................................................... 3-12 ADM7008 i 3.1.19 auto negotiation and speed configuration ........................................... 3-13
admtek inc. v1.0 3 . 2 mac interface ............................................................................................... 3-13 3.2.1 reduced media indepen d ent interfa ce (rmii) ...................................... 3-14 3.2.2 r e c e i v e p a t h f o r 1 0 0 m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.2.3 r e c e i v e p a t h f o r 1 0 m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.2.4 transmit path for 100m ........................................................................ 3-16 3.2.5 transmit path for 10m .......................................................................... 3-16 3.2.6 serial and source synchronous medi a independent interface .............. 3-17 3.2.7 100m receive path ................................................................................ 3-18 3.2.8 10m receive path .................................................................................. 3-19 3.2.9 100m transmit path .............................................................................. 3-20 3.2.10 10m transmit path ................................................................................ 3-20 3 . 3 led display .................................................................................................. 3-21 3.3.1 single color led ................................................................................... 3-21 3.3.2 dual color led ..................................................................................... 3-23 3.3.3 serial output led status ...................................................................... 3-23 3.3.4 rmii mod e (rsmode1 = 1) ................................................................. 3-24 3.3.5 smii/ss_smii mode (rsmode1 = 0) .................................................. 3-24 3 . 4 managem e nt register access ........................................................................ 3-24 3.4.1 preamble suppression ........................................................................... 3-25 3.4.2 reset operation ..................................................................................... 3-25 3 . 5 power managem e nt ....................................................................................... 3-26 3.5.1 medium detect power saving ................................................................ 3-26 3.5.2 transmit power saving .......................................................................... 3-27 3 . 6 voltage regulator .......................................................................................... 3-28 chapter 4 register description .................................................................................... 4-1 4 . 1 register mapping ............................................................................................. 4-1 4 . 2 register bit mapping ....................................................................................... 4-2 4.2.1 register #0h -- control register .............................................................. 4-2 4.2.2 register #1h ? status register ................................................................. 4-2 4.2.3 register #2h ? phy id register (002e) .................................................. 4-2 4.2.4 register #3h ? phy id register (cc11) ................................................. 4-2 4.2.5 register #4h ? advertisement register .................................................... 4-2 4.2.6 register #5h ? link partner ability r e gister ........................................... 4-2 4.2.7 r e g i s t e r # 6 h ? a u t o n e g o t i a t i o n e x p a n s i o n r e g i s t e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.8 register #7h ? # fh reserved .................................................................. 4-2 4.2.9 register #10h ? phy con figuration register .......................................... 4-2 4.2.10 register #11h ? 10m con figuration register .......................................... 4-3 4.2.11 register #12h ? 100m configuration register ........................................ 4-3 4.2.12 register #13h ? led con figuration register .......................................... 4-3 4.2.13 register #14h ? interrupt enable register .............................................. 4-3 4.2.14 register #16h ? phy ge neri c status register ......................................... 4-3 4.2.15 register #17h ? phy spe cifi c status register ......................................... 4-3 4.2.16 register #18h ? recommend value storage register ............................. 4-3 4.2.17 register #19h ? interrupt status register ................................................ 4-3 4.2.18 register #1d h ? receive error counter .................................................. 4-4 ADM7008 ii 4.2.19 register #1eh ? chip id (8888 ) ............................................................... 4-4
admtek inc. v1.0 4.2.20 register #1fh ?total interrupt status (only for port 0) .......................... 4-4 4 . 3 r e g i s t e r d e s c r i p t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.1 control (register 0h) ............................................................................... 4-4 4.3.2 status (register 1h) .................................................................................. 4-6 4.3.3 phy identifier register (register 2h) ...................................................... 4-8 4.3.4 phy identifier register (register 3h) ...................................................... 4-8 4.3.5 advertisement (register 4h) ..................................................................... 4-9 4.3.6 auto negotiation link p a rtner ability (register 5h) ............................. 4-10 4.3.7 auto negotiation expansion regi ster (register 6h) .............................. 4-11 4.3.8 register reserved (register 7h-fh) ....................................................... 4-11 4.3.9 generic phy configuration register (register 10h) ............................ 4-11 4.3.10 phy 10m module configuration register (register 11h) .................... 4-12 4.3.11 phy 100m module control register (register 12h) ............................. 4-13 4.3.12 led configuration register (register 13h) .......................................... 4-13 4.3.13 interrupt enable register (register 14h) .............................................. 4-15 4.3.14 phy generic status register (register 16h) ......................................... 4-16 4.3.15 phy specific status register (register 17h) ......................................... 4-17 4.3.16 phy recommend value status register (register 18h) ........................ 4-18 4.3.17 interrupt status register (register 19h) ................................................ 4-18 4.3.18 receive error counter register (register 1dh) .................................... 4-19 4.3.19 chip id register (register 1fh) ............................................................ 4-20 4.3.20 per port interrupt and r evision id register (register 1eh) ................. 4-20 chapter 5 electrical s p ecification ................................................................................ 5-1 5 . 1 d c c h a r a c t e r i z a t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 absolute maximum rating ....................................................................... 5-1 5.1.2 recommended operatin g condition s ...................................................... 5-1 5.1.3 dc electrical characteristic s for 3.3v operation .................................. 5-1 5 . 2 a c c h a r a c t e r i z a t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2.1 xi/osci (cr y stal/oscillator) timing ....................................................... 5-2 5 . 3 rmii tim i ng .................................................................................................... 5-3 5.3.1 refclk input timing (when refclk_sel is set to 1) ....................... 5-3 5.3.2 refclk output timing (when refclk_sel is set to 0) ..................... 5-4 5.3.3 rmii trans mit timing ............................................................................. 5-5 5.3.4 rmii receive timing ............................................................................... 5-6 5 . 4 smii clock tim i ng .......................................................................................... 5-7 5.4.1 refclk input timing (when refclk_sel is set to 1) - ..................... 5-7 5.4.2 refclk output timing (when refclk_sel is set to 1) ..................... 5-8 5.4.3 smii/ss_smii transmit timing ............................................................... 5-9 5.4.4 smii/ss_smii receive timing ............................................................... 5-10 5 . 5 serial managem e nt inte rface (mdc/mdio) timing .................................... 5-11 5 . 6 power on configuration tim i ng ................................................................... 5-12 c h a p t e r 6 p a c k a g i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 ADM7008 iii
admtek inc. v1.0 list of figures fi gu re 1- 1 a d m 70 0 8 b l oc k di ag ram ....................................................................................... 1-3 fi gu re 2- 1 a d m 70 0 8 pi n as si gnm ent ...................................................................................... 2-1 fi gu re 3- 1 a d m 70 0 8 s w i t c h a ppl i cat i o n ( 1 0/ 1 00m tp m ode ) ..................................................... 3-1 fi gu re 3- 2 1 0 0 b ase-x b l ock di ag ram and dat a pat h ................................................................... 3-3 fi gu re 3- 3 1 0 b a se-t b l oc k di agram and dat a pat h ................................................................... 3-10 fi gu re 3- 4 r m ii si g n al di a g r a m ........................................................................................... 3-14 fi gu re 3- 5 r m ii r ece pt i o n w i t h o u t e r r o r ............................................................................... 3-15 fi gu re 3- 6 r m ii r ece pt i o n w i t h fal s e c a r r i e r ( 1 00m o n l y ) ........................................................ 3-15 fi gu re 3- 7 r m ii r ece pt i o n w i t h sy m bol err o r ......................................................................... 3-15 figure 3-8 10m rm ii recei ve diagram .................................................................................. 3-16 figu re 3- 9 1 0 0 m rm ii t r a n s m it diagram ............................................................................... 3-16 figu re 3- 1 0 10 m rm ii t r a n s m it diagram ............................................................................... 3-17 figu re 3- 1 1 s m ii sig n al dia g ram .......................................................................................... 3-18 figure 3-12 s s _ smii signal diagram ..................................................................................... 3-18 fi gu re 3- 1 3 10 0m sm ii r ece i v e ti m i ng di a g ram .................................................................... 3-18 figure 3-14 100m ss_smi i receive timing diagram ............................................................... 3-18 figure 3-15 10m smii receive tim i ng dia g ram ...................................................................... 3-19 figure 3-16 10m ss_smi i r eceive tim i ng diagram ................................................................. 3-19 fi gu re 3- 1 7 10 0m sm ii tra n sm i t tim i ng d i agram ................................................................... 3-20 fi gu re 3- 1 8 10 0m s s _ s m i i tran sm it tim i ng di a g ram .............................................................. 3-20 fi gu re 3- 1 9 10 m sm ii tra n s m i t tim i ng di agram ..................................................................... 3-20 fi gu re 3- 2 0 10 m ss _sm i i t r ansm i t tim i ng di ag ram ............................................................... 3-21 fi gu re 3- 2 1 st r e am led un de r r m i i m o de ............................................................................. 3-24 fi gu re 3- 2 2 st r e am led un de r sm ii/ ss _sm ii m o de ................................................................ 3-24 figure 3-23 smi read operation ........................................................................................... 3-25 figu re 3- 2 4 s m i write o p er ation ........................................................................................... 3-25 fi gu re 3- 2 5 m e di um det ect po wer m a na ge m e nt fl ow c h art ....................................................... 3-27 fi gu re 3- 2 6 l o w p o wer li n k pul s e d u ri n g t x fo r p o wer m a nagem e nt ......................................... 3-28 f i g u r e 3 - 27 exter n al pn p pow e r t r an s i s t or d i agr a m ................................................................. 3-29 fig u re 5 - 1 c r ystal/oscillato r ti m i n g ........................................................................................ 5-2 fi gu re 5- 2 r e fc lk i n p u t ti m i ng ........................................................................................... 5-3 fi gu re 5- 3 r e fc lk o u t p ut tim i ng ......................................................................................... 5-4 fi gu re 5- 4 r m ii tra n sm i t tim i ng ............................................................................................ 5-5 figure 5-5 rm ii recei ve timing ............................................................................................. 5-6 fi gu re 5- 6 r e fc lk i n p u t ti m i ng ........................................................................................... 5-7 fi gu re 5- 7 sm ii/ ss _sm i i r e fc lk o u t p u t tim i ng .................................................................... 5-8 fi gu re 5- 8 sm ii/ ss _sm i i tr ansm i t tim i ng ............................................................................... 5-9 figure 5-9 sm ii/ss_s m i i receive tim i ng .............................................................................. 5-10 figure 5-10 se rial managem e nt interface (m dc/mdio) ti ming ................................................. 5-11 fi gu re 5- 1 1 p o wer o n c o n f i g urat i o n ti m i ng ........................................................................... 5-12 ADM7008 iv
admtek inc. v1.0 list of tables tabl e 3- 1 l o o k - u p ta bl e f o r t r ansl at i n g 5b sym bol s i n t o 4 b ni b b l e s. ............................................ 3-5 tabl e 3- 2 c h a nnel c o nfi g u r a t i o n ........................................................................................... 3-17 tabl e 3- 3 r ece i v e dat a enc o di n g fo r sm ii/ ss_ sm i i m o d e ........................................................ 3-19 tabl e 3- 4 s p ee d le d di s p l a y ............................................................................................... 3-21 tabl e 3- 5 du pl ex le d di s p l a y ............................................................................................. 3-22 tab l e 3 - 6 activ ity/lin k led disp lay ..................................................................................... 3-22 tabl e 3- 7 di ff erent b l i n ki n g ti m e f o r d i ff er en t sp eed .............................................................. 3-22 tabl e 3- 8 c a bl e di st ance le d di spl a y ................................................................................... 3-22 tabl e 3- 9 s p ee d le d di s p l a y ............................................................................................... 3-23 tabl e 3- 10 act i vi t y / l i nk le d di spl a y ................................................................................... 3-23 tabl e 5- 1 el ec t r i cal abs o l u t e m a xi m u m r a ti ng .......................................................................... 5-1 tab l e 5 - 2 reco mmen d e d operatin g con d itio ns .......................................................................... 5-1 table 5-3 dc electrical charact eristics for 3 . 3 v op eration ........................................................... 5-1 tab l e 5 - 4 crystal/oscillato r ti m i n g ......................................................................................... 5-2 tabl e 5- 5 r e f c lk in p u t ti m i ng ............................................................................................ 5-3 tabl e 5- 6 r e f c lk out put t i m i ng .......................................................................................... 5-4 tabl e 5- 7 r m i i t r ansm i t tim i ng ............................................................................................. 5-5 table 5-8 rmii receive timing .............................................................................................. 5-6 tabl e 5- 9 r e f c lk in p u t ti m i ng ............................................................................................ 5-7 tabl e 5- 10 sm ii/ ss _sm i i r e fc lk o u t p u t tim i ng ................................................................... 5-8 tabl e 5- 11 sm ii/ ss _sm i i tr ansm i t tim i ng .............................................................................. 5-9 table 5-12 sm ii/ss_s m i i receive tim i ng .............................................................................. 5-10 table 5-13 se rial managem e nt interface (m dc/mdio) ti ming .................................................. 5-11 tabl e 5- 14 p o wer o n c o n f i g urat i o n ti m i ng ............................................................................. 5-12 ADM7008 v
ADM7008 product review chapter 1 pr oduct overview 1.1 overview the ADM7008 is a single chip eight port 10/1 00m phy, which is designed for today?s low cost and low power dual speed application. it supports eight auto sensing 10/100 mbps por ts with on-chip clock recovery and base line wander correction in cluding in tegrated mlt - 3 functionality for 100 mbps operation. it also supports manchester code c onverter with on chip clock recovery circuitry for 10 mbps functionality, provides red u ced mii (rmii), se rial mii (s mii) and s ource synchronous mii (ss_ smii) in terface to fac ilitate h i gh port count switch sys t em application and reduce the pin num ber sim u ltaneously. for today?s inform ation application (ia), a d m7008 also supports ?auto cross ove r detection ? f unction to e lim inate the techni cal barrier between networking and the end user. w ith the aid of this auto cross over detection function, plug-n- play features can be easily applied to ia relative products. to m a ke the user interface as friendly as possible, ADM7008 provid e s cable len g th inform ation for cat5 cable and als o detect s th at th e wir e connection on the rj -4 5 is broken or not. this function is specifically helpful in system debugging, especially for high port count approach system debugging. the m a jor design goal for ADM7008 is to re duce the pow er consum ption and syste m radiation for the whole system . w ith the aid of this low power consumption and low radiation chip, fan and on-system power s upply can be rem oved to save the total m a nu facture cost and m a ke soho ap plication achievable. admtek inc. 1-1
ADM7008 product review 1.2 features x ieee 802.3 com p atible (2000 edition ) 10b ase-t and 100base-t physical layer interface an d ansi x3.263 tp-pmd com p atible transceiver. x eight-port, single chip, integrated physical layer and transceive rs for 10base-t and 100base-tx function. x reduced mii (rmii), serial mii (s mii) and source synchronous mii (ss_smii) for high port count switch. x built- in 10 mbit transm it f ilter. x 10 mbit pl l, exceedin g tolerances for both pream b le and data jitter. x 100mbit pl l, com b ined with the dig ital ad aptive equalizer an d perform a nce exceeds 140 m e ters for utp 5. x 125mhz clock generator and tim i ng recovery. x integrated b a se line w a nder correction. x carrier integrity mon itor function supported. x supports fefi when auto negotiation is disabled. x supports auto cross over detection function for plug-and-play. x ieee 802.3u clause 28 com p liant auto negot iation for full 10 mbps and 100 mbps control. x supports programm a ble led for different switc h application and power on led self test. x supports cable length indication both in mii register and l e d (programmable). x supports cable broken auto detection func tion and indicate cable broken location. x supports pecl interface for fiber connection. x built-in 3.3 v to 1.8v regulato r control sign al. x built- in clo c k generato r and power on reset signal to sav e system cost. x 128 pqfp with 1.8v/3.3v power supply. x support power saving function. x support parallel/serial led output. admtek inc. 1-2
ADM7008 product review 1.3 block diagram figure 1-1 adm7 008 block diagr a m 1.4 abbreviations ansi am erican national stan dards ins t itu t e ber bit erro r rate col collis ion crs carrier sense crsdv carrier sense and data valid ctl crystal dsp digita l sign al proces sor dupcol duplex and collis ion esd end of stream delim iter fefi far end fault indication admtek inc. 1-3 po r t 0 po r t 1 ... po r t 7 clo c k g e ne ra t o r tw i s t e d pa i r in te r f a c e m a c in te r f a c e le d di sp l a y sm i r m ii /s m i i / ss _sm i i se r i a l / p a r a lle l le d md c / m d i o po w e r m anagem ent mi i au t o n egot i a ti on c abl e b r ok en de t e c t o r 100m m odul e 10m m odul e dr i v e r m i i r m i i m i i s s _ s m i i m i i s m i i v o l t age r egul at or
ADM7008 product review fifo first in first out flp fast link pulse fx fiber ia inform ation application lfsr linear feed back shifter register llp low-power link pulse lnkact link and activity lvttl ttl level mac media access controller md medium detect mdc managem e nt data clock mdio managem e nt data input/output mii media ind e p e ndent in terface nrz none return to zero nrzi none return to zero inverter op operation c ode pcs physical coding sub-layer pecl pseudo em itter couple l ogic phy physical layer phyaddr phy address pma physical medium attachm e nt pmd physical medium dependent pnp a type of transistor pqfp plastic quad flat pack refcl k reference clock rf rem o te fault rmii reduced media indep e n d ent in terface rsmode rmii/smii/ss_smii mode select rxc receive clo c k rxd receive data rxdv receive data valid rxer receive data error rxn receive negative (anal og receive d i fferential signal) rxp receive pos itiv e (analo g rece ive dif f erentia l sig n al) rx_sync receive syn c hronous sdn signal detect negati ve (fiber signal detect) sdp signal detect positi ve (fiber signal detect) selfx select f i ber smi serial managem e nt interface smii serial media independent interface soho sm all offic e and hom e office sqe signal quality error ssd start of str e am delim iter ss_smii source synchronous me dia independent interface sync synchronous admtek inc. 1-4 ta turn around
ADM7008 product review tdr tim e domain reflectometry tp twisted pair tp-pmd twisted pair physical medium depe ndent ttl transistor transistor logic txc transm ission clock (m ii) txclk transm ission clock (smii/ss_sm ii) txd transm ission data txen transm ission enable txer transm ission error txn transm ission negative txp transm ission positive /j/k 5b signal to detec t the s t art of a f r ame /t/r 5b signal to detect the end of a fra m e 1.5 conventi ons 1.5.1 data lengths qword 64-bits dword 32-bits word 16-bits byte 8 bits nibble 4 bits 1.5.2 register type descriptions register typ e description ro read only r/ w read and write capable sc self -clea r in g ll latching low, unlatch on read lh latching high, unlatch on read cor clear on read 1.5.3 pin type descriptions pin type description i: input o: output i/o: bi-dire c tion a l od: open drain sche: schm itt trig ger pu: pull up admtek inc. 1-5 pd: pull down
ADM7008 interf ace description chapter 2 interface description 2.1 pin diagram v c c 3 o v c c a d r xn0 v c c a d g n d o v c c 3 o vcc ad vcc ad vcc ad vcc 3 o g n d o r x d 1 _ p 0/ s p d l e d _p 0 ( r e c _10m _ p 0) r xd0 _ p 0 / r x d_ p 0 ( t e s t s e l 0 ) c r s d v _p 0 ( s e l f x 0) t xd1 _ p 0 / l nk ac t _ p 0 t xd0 _ p 0 / t x d _ p 0 tx en _ p 0 / n a re f c l k g n d i k s c an_ m ode s c an_ e n xi xo c o n t r o l rt x v c c p l l 2 v c c a 2 tx p 0 t x n 0 rx p 0 adm 7 0 0 8 qf p 1 2 8 re v i s i o n a1 tx en _ p 6 / n a t xd0 _ p 6 / t xd_ p 6 t x d 1_p 6 / l n k a c t _p 6 ( r sm o d e 0 ) c r sd v _ p6 / n a ( l e d m d 0 ) r xd0 _ p 6 / r xd_ p 6 ( r e c _ 10m _p 6) r x d 1_p 6/ s p e e d _ l e d _p 6 tx en _ p 7 / n a t xd0 _ p 7 / t xd_ p 7 t x d 1_p 7 / l n k a c t _p 7 ( f x _ p aus e ) c r s dv_ p 7 ( e n _ aut om di x ) r xd0 _ p 7 / r x d_ p 7 ( r e c _ 10m _p 7) r x d 1_p 7/ s p e e d _ l e d _p 7 led _ c lk led _ d a t a re f c l k _ s e l rs t _ n g n d i k v c c 2 i k p hya ddr 1 r s m ode 1 v c c a 2 tx p 7 rx n 1 rx p 1 tx n 1 tx p 1 vcc a2 tx p 2 tx n 2 rx p 2 rx n 2 rx n 3 rx p 3 tx n 3 tx p 3 vcc a2 tx p 4 tx n 4 rx p 4 rx n 4 rx n 5 rx p 5 tx n 5 tx p 5 vcc a2 tx p 6 tx n 6 rx p 6 rx n 6 rx n 7 rx p 7 md c md i o tx en _ p 1 / n a tx d 0 _ p 1 / tx d _ p 1 t x d 1_p 1/ l n k a c t _p 1 c r s dv_ p 1 / n a ( s e l f x1 ) r xd0 _ p 1 / r xd_ p 1 ( t e s t s e l 1 ) r x d 1 _p 1/ s p d l e d _p 1 ( r e c _10m _p 1) tx en _ p 2 / n a tx d 0 _ p 2 / tx d _ p 2 t x d 1_p 2/ l n k a c t _p 2 c r s d v _ p 2 ( f xd up l e x) r xd0 _ p 2 / r x d_ p 2 ( p hy add r 0 ) r x d 1 _p 2/ s p d l e d _p 2 ( r e c _10m _p 2) gn d i k vcc2 i k t x e n _p 3/ t x _s y n c tx d 0 _ p 3 / tx d _ p 3 t x d 1_p 3/ l n k a c t _p 3 c r s d v _ p 3 / r x _ s y n c ( t es ts el2 ) r x d 0 _ p 3 / r xd_ p 3 ( a ne nd i s ) r x d 1 _ p 3 / s p d l e d _p 3 ( r e c _ 10m _ p 3) gn d o tx e n _ p 4 / tx _ c lk tx d 0 _ p 4 / tx d _ p 4 t x d 1_p 4/ l n k a c t _p 4 c r s d v _ p 4/ r x _c l k ( d l y 2n s ) r xd0 _ p 4 / r xd_ p 4 ( t p d up l e x) r x d 1 _ p 4 / s p d l e d _p 4 ( r e c _ 10m _ p 4) gn d i k vcc2 i k tx en _ p 5 / n a tx d 0 _ p 5 / tx d _ p 5 t x d 1_p 5/ l n k a c t _p 5 c r sd v _ p5 / n a ( t p_ pa u s e ) r x d 0_p 5/ r x d _ p 5 ( p w s a v e _ d i s ) r x d 1 _ p 5 / s p d l e d _p 5 ( r e c _ 10m _ p 5) 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 6 7 5 4 3 2 1 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 4 5 4 4 4 3 4 2 4 1 4 0 3 9 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 100 101 102 11 1 11 8 11 7 11 6 11 5 11 4 11 3 11 2 11 9 12 0 12 3 12 2 12 1 12 8 12 7 12 6 12 5 12 4 11 0 10 9 10 8 10 7 10 6 10 5 10 4 10 3 g n d r c v g n d r t t xn7 g n d r t gn d r t gn d r t gn d r t gn d r t gn d r t gn d r t figure 2-1 adm7 008 pin assignm ent admtek inc. 2-1
ADM7008 interf ace description 2.2 pin description note: for those pins, which ha ve m u ltiple f unctions, p i n nam e is separated by slash (?/?). if not specified, all signals are default to digital signals. please refer to section ?1 .5.3 pin type descriptions ? for an explanation of pin abbrevia tion s . 2.2.1 tw isted pair interface, 32 pins pin # pin name ty p e des c ription 123, 5, 7, 17 19, 29, 31, 41 t x p [ 0 : 7 ] o , analog twi s ted pair tran smit out put positive. 124, 4, 8, 16 20, 28, 32, 40 t x n [ 0 : 7 ] o , analog twi s ted pair tran smit out put neg a tive. 126, 2, 10, 14 22, 26, 34, 38 rxp[0:7] i, analog twi s ted pair re ceive input positive. 127, 1, 11, 23 23, 25, 35, 37 rxn[0:7] i, analog twi s ted pair re ceive input negative. 2.2.2 ground and po w er, 20 pins pin # pin name ty p e des c ription 125, 3, 9, 15, 21, 27, 33, 39 g n d r t a n a l o g gro und analog g r ou nd pad 118, 128, 12, 24, 36 vcca d a n a l o g power analog 3.3v powe r 122, 6, 18, 30 , 42 v c c a 2 a n a l o g power analog 1.8v powe r 1 2 0 g n d r c v a n a l o g gro und analog g r ou nd used by cl ock gen e rato r modul e 1 2 1 v c c p l l 2 a n a l o g power analog 1.8v powe r used b y clock gen e r ator m odul e 2.2.3 mode setting pin # pin name ty p e des c ription 43 rsmode1 i, pd rmii and smii/ss_ smii mode select signal. dedi cate d input provid ed by adm7 008 to d e termin e the interfa c e: 0: smii or ss_smii interface (se e crs d v_p6 po we r on setting for more detail) 1: rmii interfac e 2.2.4 clock inpu t select admtek inc. 2-2 pin # pin name ty p e des c ription 48 refclk_se l i, pd xi/xo and re fclk cl ock sele ct sig nal. dedi cated in put provid ed by adm7 008 to d e termin e the clo ck sou r ce for adm70 08. 0: ADM7008 will use xi/xo as cl ock source for internal clock generator. in this mode, refclk (pi n 112 ) will ou tput 50m clock in rmii mode (rsmode1 i s set to 1) and 1 25m cl ock in either smii or ss_smii mode (rsmode1 i s set to 0) \ 1: ADM7008 will use the input of refclk (pin 112) as the
ADM7008 interf ace description pin # pin name ty p e des c ription c l oc k source for internal c l oc k generat o r. not e : that wh en rsmo de 1 is set to 1 (rmii mode ), the input of refclk shoul d be 50m; whe n rsmo de1 is set to 0 (smii or ss_smii mode) the c l oc k input on refclk shoul d be 125 m 2.2.5 clock inpu t, 3 pins pin # pin name ty p e pin descrip tion 115 xi/osci i, ctl cry s tal/oscill ator inp u t. refclk_se l = 0: 25m crystal/oscillat o r input. refclk_se l = 1: leave unconn ecte d 116 xo o, ctl cry s tal outpu t. when 25m o scill ator i s use d , this pin shoul d be left uncon ne cted. see xi/osci de scrip t ion above. 1 1 1 r e f c l k i / o , 16ma lvttl refe ren c e cl ock. functio n on this pin i s highly de pe nded u pon the setting on refclk _sel and rsm o de1: refc lk_se l rsmo de1 refc lk (di r e c tion/frequ ency ) 0 0 output/125 mhz 0 1 output/50 mhz 1 0 in put/125 m h z with maximu m 100p pm 1 1 in put/50 mhz with maximum 100p pm 2.2.6 rmii/smii interface, 48 pins admtek inc. 2-3 pin # pin name ty p e pin descrip tion 51, 52 powe r on setting rec_10m _p 7, en_automdix rmii mode rxd[1:0]_p7 smii/ss_smi i mode spdled_p7, smii_rxd_p 7 i/o, 8ma, pd/pu rec_10m: value on rxd1_p7 will b e latche d by adm700 8 duri ng po we r on re set a s port 7 10m re-comm and val ue. 0: recomme nd port 7 to operate in 100 m mode 1: recomme nd port 7 to operate in 10m mode a uto mdix enable sign al: value on rxd0_p 7 will be latched by adm70 08 du ring p o wer on reset as auto mdix functi on co ntrol sign al. 0: disa ble all port s ? auto mdix function. 1: enable all port s ? auto mdix function. port 7 rmii rec e ive data. rxd[ 1:0] are the port 7 out put di- bits syn c h r on ously to ref c lk. upo n a s sertio n of crsdv_p, rxd0 and rxd1 re main a t 00 until valid data is outpu t from the fifo onto rxd. 01 on rxd1 an d rx d0 indi cate s the sta r t of valid data. if a false carrie r or a symbol error i s dete c ted, rxd1 and rx d0 a r e set to 10 for the duratio n of the activity. note that in 100mb / s mode rxd can chan ge once pe r re fclk cycle, whe r ea s in 10m b/s mode rxd m u st be hel d st eady for 10 co nsecutive refclk cy cle s . port 7 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to smii refclk (pin 70 ). in 100mb/s mode, rxd0 output s a ne w 10 -bi t segme n t sta r ting with sy nc. in 10mb/ s mode , rxd0 mu st rep eat ea ch 1 0 bits se gme n t 10 times. rxd1 for the de sign ated po rt is a c ted a s spee d status led for po rt 7.
ADM7008 interf ace description pin # pin name ty p e pin descrip tion admtek inc. 2-4 ss_smii mode spdled_p7, sss_smii_rxd _p7 port 7 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 7. 5 3 p o w e r o n setting fx_pause rmii mode crs dv_p7 smii/ss_smi i mode n/a i, lvttl, pd o, 8ma fiber pause recommend value. value on this pin will be latche d by adm7 008 d u ri ng po we r on reset a s fibe r port (se e selfx powe r on setting for more detail) pause ca pab ility cont rol si gnal . 0: pause off for all fiber p o rts 1: pause o n for all fiber p o rts port 7 ca rrie r sense/ re cei v e data valid . crsdv_p7 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p7 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p7 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv_p7 i s asse rted synch r o nou sly to refclk. the toggling of crsdv_p 7 on the first and se con d di-bit contin ue s until all the data in the fifo is presente d onto rx d. crs dv_p7 i s asse rted for the durat io n of carrie r acti vity for a false carrie r e v ent. not used in s m ii/ss_smii mode 54, 55 rmii mode txd[1:0]_p7 smii mode lnkact_p7, smii_txd_p 7 smii mode lnkact_p7, sssmii_txd_p7 i, ttl, pd port 7 rmii tran smit data. transmit data for port 7 in put the di-bit s that re tran smitted a nd are driven synchrono usl y to refclk. not e : that in 100m b/s mod e , txd can chang e on ce p e r refclk cycl e, whe r ea s in 10mb/s mo d e , txd must be held steady for 1 0 con s e c utiv e refclk cycl es. link a nd acti vity led/port 7 sm ii transmit data. txd0 for port 7 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to smii_refclk (pi n 70 ). in 100mb/s mode, txd0 inputs a new 1 0 -bit se gment sta r tin g with sync. in 10mb/s mode, txd0 mu st repeat ea ch 1 0 -bit segme n t 10 times. txd1_p 7 acts a s port 7 link/activity led in both smii and ss_smii mode. see l e d de scriptio n for more de tail. link a nd acti vity led/port 7 ss_smii transmit data. txd0 for port 7 inp u ts the data that is tran smitted and is d r iven synchrono usl y to txclk (pin 70 ). in 100mb/s mo de, txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 5 6 r m i i m o d e txen_p7 smii/ss_smi i low i, ttl port 7 tran smit enable. tran smit ena b le for po rt 7 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refclk. tied to lo w. txen_p7 sho u ld be ti ed to low for norm a l ope ration.
ADM7008 interf ace description pin # pin name ty p e pin descrip tion admtek inc. 2-5 59, 60 power on setting rec_10m _p 6, dua lled rmii mode rxd[1:0]_p6 smii mode spdled_p6, smii_rxd_p 6 ss_smii mode spdled_p6, sssmii_rxd_p 6 i pd, pd, o, 8ma o, 8ma o, 8ma rec_10m: value on rxd1_p6 will b e latche d by adm700 8 duri ng po we r on re set a s port 6 10m re-comm and val ue. 0: recomme nd port 6 to operate in 100 m mode 1: recomme nd port 6 to operate in 10m mode dual colo r l e d mode. value on rxd0_p6 will b e latche d by adm70 08 du ring p o wer on reset to form led co ntrol sign al. value on thi s pin will affect the output value on seri al led output. 0: single col o r 3 bits/p ort se rial stream (default valu e) 1: dual colo r 3 bits/po r t serial stre am port 6 rmii rec e ive data. rxd[ 1:0] are the port 6 out put di- bits syn c h r on ously to ref c lk. upo n a s sertio n of crsdv_p, rxd0 and rxd1 re main a t 00 until valid data is outpu t from the fifo onto rxd. the start of valid data is indicated b y 01 on rxd1 and rxd0. if a false ca rrie r or a symbol e r ror i s detecte d, rx d1 an d rx d0 are set to 10 for the dura t ion of the activity. note that in 100m b/s mod e rx d ca n ch ang e once pe r refclk cycl e, whe r ea s in 10mb/s mo d e rxd mu st be held steady for 1 0 con s e c ut ive refclk cycl es. port 6 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to smii refclk (pin 70 ). in 100mb/s mode, rxd0 output s a ne w 10 -bi t segme n t sta r ting with sy nc. in 10mb/ s mode , rxd0 mu st rep eat ea ch 1 0 bits se gme n t 10 times. rxd1 for the de sign ated po rt is a c ted a s spee d status led for po rt 6. port 6 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 6. 61 power on setting rsmo de0 rmii mode crs dv_p6 i, lvttl, pd o, 8ma rmii/smii/ss _ smii configuration bit 0. value on thi s pin will be latch ed by adm700 8 du ring p o wer on reset as interface config uration bit 0. combi ned with rs mode1 (pin 43), thre e possibl e interface s are pro v ided by adm700 8 rsmode[1:0] interfac e 00 smii 01 ss_smii 1x rmii port 6 ca rrie r sense/ re cei v e data valid . crsdv_p6 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p6 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p6 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv p6 i t d h l t refclk th
ADM7008 interf ace description pin # pin name ty p e pin descrip tion admtek inc. 2-6 smii/ss_smi i mode n/a crs dv_p6 i s asse rted synch r o nou sly to refclk. the toggling of crsdv_p 6 on the first and se con d di-bit contin ue s until all the data in the fifo is presente d onto rx d. crs dv_p6 i s asse rted for the durat io n of carrie r acti vity for a fals e carrier event. not used. not used in s m ii/ss_smii mode 62, 63 rmii mode txd[1:0]_p6 smii mode lnkact_p6, smii_txd_p 6 ss_smii mode lnkact_p6, sssmii_txd_p6 i, lvttl, pd, pd port 6 rmii tran smit data. transmit data for port 6 in put the di-bit s that re tran smitted a nd are driven synchrono usl y to refclk. no te that in 100mb/s mod e , txd ca n ch an ge on ce per refclk cycle, whe r ea s in 10m b/s mode, txd must be held ste ady for 10 con s e c utive refcl k cycle s . link a nd acti vity led/port 6 sm ii transmit data. txd0 for port 6 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to smii_refclk (pi n 70 ). in 100mb/s mode, txd0 inputs a new 1 0 -bit se gment sta r tin g with sync. in 10mb/s mode, txd0 mu st repeat ea ch 1 0 -bit segme n t 10 times. txd1_p 6 act s as po rt 6 link/activity led in both smii and ss_smii mode. see led description f o r mo re detail . link a nd acti vity led/port 6 ss_smii transmit data. txd0 for port 6 inp u ts the data that is tran smitted and is d r iven synchrono usl y to txclk (pin 70 ). in 100mb/s mo de, txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 64 rmii mode txen_p6 smii/ss_smi i low i, ttl port 6 tran smit enable. tran smit ena b le for po rt 6 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refc lk. tied to lo w. txen_p6 sho u ld be ti ed to low for norm a l ope ration in b o th smii and ss_smii mode. 65, 66 power on setting rec_10m _p 5, pwsave_di s rmii mode rxd[1:0]_p5 i, pd, pd o, 8ma rec_10m: value on rxd1_p5 will b e latche d by adm700 8 duri ng po we r on re set a s port 5 10m re-comm and val ue. 0: recomme nd port 5 to operate in 100 m mode (def ault) 1: recomme nd port 5 to operate in 10m mode lower p o wer link pul s e fu nction (power saving, llp) disa ble. value on rxd1 will b e latche d by adm 7008 d u ri ng p o we r on re set as p o wer saving di sable si gnal. (see lo wer p o we r lin k pulse fu nctio n description for more deta il) 0: power sav i ng enabl e 1: power sav i ng disable (default) port 5 rmii rec e ive data. rxd[ 1:0] are the port 5 out put di- bits syn c h r on ously to ref c lk. upo n a s sertio n of crsdv_p, rxd0 and rxd1 re main a t 00 until valid data is outpu t from the fifo onto rxd. 01 on rxd1 an d rx d0 indi cate s the sta r t of valid data. if a false carrie r or a symbol error i s dete c ted, rxd1 and rx d0 a r e set to 10 for the duratio n of the activity. note that in 100mb / s mode rxd can chan g e once p er r e f c l k
ADM7008 interf ace description pin # pin name ty p e pin descrip tion admtek inc. 2-7 smii mode spdled_p5, smii_rxd_p 5 ss_smii mode spdled_p5, sssmii_rxd_p 5 cycle, whe r ea s in 10m b/s mode rxd m u st be hel d st eady for 10 co nsecutive refclk cy cle s . port 5 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to smii refclk (pin 70 ). in 100mb/s mode, rxd0 output s a ne w 10 -bi t segme n t sta r ting with sy nc. in 10mb/ s mode , rxd0 mu st rep eat ea ch 1 0 bits se gme n t 10 times. rxd1 for the de sign ated po rt is a c ted a s spee d status led for po rt 5. port 5 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 5. 67 power on setting tp_pause rmii mode crs dv_p5 smii/ss_smi i mode n/a i, lvttl, pu o, 8ma twi s ted pair pause reco mmend val u e. value on this pin will be latch ed by adm700 8 du ring p o wer on reset as twi s ted pai r port (se e selfx power o n setting for more d e tail) p ause capability control signal. 0: pause off for all twi s ted pair p o rts 1: pause o n for all twi s ted pair p o rts port 5 ca rrie r sense/ re cei v e data valid . crsdv_p5 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p5 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p5 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv_p5 i s asse rted synch r o nou sly to refclk. the toggling of crsdv_p 5 on the first and se con d di-bit contin ue s until all the data in the fifo is presente d onto rx d. crs dv_p5 i s asse rted for the durat io n of carrie r acti vity for a fals e carrier event. not used. not used in s m ii/ss_smii mode 68, 69 rmii mode txd[1:0]_p5 smii mode lnkact_p5, smii_txd_p 5 i, ttl, pd port 5 rmii tran smit data. transmit data for port 5 in puts the di-bit s that re tran smitted a nd are driven synchrono usl y to refclk. no te that in 100mb/s mod e , txd ca n ch an ge on ce per refclk cycle, whe r ea s in 10m b/s mode, txd must be held ste ady for 10 con s e c utive refcl k cycle s . link a nd acti vity led/port 5 sm ii transmit data. txd0 for port 5 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to smii_refclk (pi n 70 ). in 100mb/s mode, txd0 inputs a new 1 0 -bit se gment sta r tin g with sync. in 10mb/s mode, txd0 mu st repeat ea ch 1 0 -bit segme n t 10 times. txd1_p 5 act s as po rt 5 link/activity led in both smii and ss_smii mode. see led description f o r mo re detail .
ADM7008 interf ace description pin # pin name ty p e pin descrip tion admtek inc. 2-8 ss_smii mode lnkact_p5, sssmii_txd_p5 link a nd acti vity led/port 5 ss_smii transmit data. txd0 for port 5 inp u ts the data that is tran smitted and is d r iven synchrono usl y to txclk (pin 70 ). in 100mb/s mo de, txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 70 rmii mode txen_p5 smii/ss_smi i low i, ttl port 5 tran smit enable. tran smit ena b le for po rt 5 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refc lk. smii/ss_smii mode. keep low fo r no rmal op eratio n. 73, 74 power on setting rec_10m _p 4, tp_duplex rmii mode rxd[1:0]_p4 smii mode spdled_p4, smii_rxd_p 4 ss_smii mode spdled_p4, sssmii_rxd_p 4 i/o, 8ma, pd/pu rec_10m: value on rxd1_p4 will b e latche d by adm700 8 duri ng po we r on re set a s port 4 10m re-comm and val ue. 0: recomme nd port 4 to operate in 100 m mode 1: recomme nd port 4 to operate in 10m mode twi s ted pair dupl ex re co mmend val u e. value on rxd1 will be latch ed by adm700 8 du ring p o wer on reset as du pl ex re comm end v a lue for twi s t ed pai r interfa c e. 0: half dupl e x for all twiste d pair p o rts 1: full dupl ex for all twisted pair po rts port 4 rmii rec e ive data. rxd[ 1:0] are the port 4 out put di- bits syn c h r on ously to ref c lk. upo n a s sertio n of crsdv_p, rxd0 and rxd1 re main a t 00 until valid data is outpu t from the fifo onto rxd. 01 on rxd1 an d rx d0 indi cate s the sta r t of valid data. if a false carrie r or a symbol error i s dete c ted, rxd1 and rx d0 a r e set to 10 for the duratio n of the activity. note that in 100mb / s mode rxd can chan ge once pe r re fclk cycle, whe r ea s in 10m b/s mode rxd m u st be hel d st eady for 10 co nsecutive refclk cy cle s . port 4 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to smii refclk (pin 70 ). in 100mb/s mode, rxd0 output s a ne w 10 -bi t segme n t sta r ting with sy nc. in 10mb/ s mode , rxd0 mu st rep eat ea ch 1 0 bits se gme n t 10 times. rxd1 for the de sign ated po rt is a c ted a s spee d status led for po rt 4. port 4 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 4. 75 power on setting dly2 ns i, lvttl, pd refclk del a y 2ns. value on this pin will be latched by adm70 08 du ring p o wer on reset as del a y select si gna l for refclk inpu t when ref c lk _sel and rsmo de1 are both s e t to 1 (rmii interface wit h refclk as clock inp u t)
ADM7008 interf ace description pin # pin name ty p e pin descrip tion admtek inc. 2-9 rmii mode crs dv_p4 smii mode n/a ss_smii mode rxc l k o, 8ma 0: norm al re fclk cl ock p a th 1: refclk d e lay by 2 ns port 4 ca rrie r sense/ re cei v e data valid . crsdv_p4 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p4 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p4 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv_p4 i s asse rted synch r o nou sly to refclk. the toggling of crsdv_p 4 on the first and se con d di-bit contin ue s until all the data in the fifo is presente d onto rx d. crs dv_p4 i s asse rted for the durat io n of carrie r acti vity for a fals e carrier event. not used. not used in s m ii mode 125m re ceiv e clo ck. thi s pin acts a s 1 25m re ceive clo ck whe n adm7 0 08 is p r og ram m ed to ss_smii mode. all sss_smii_rxd are s y nchronous to the ris i ng edge of this clo ck. not e : that cl ock on this pin w ill not be active during power on re set due to p o we r on setting. 76, 77 rmii mode txd[1:0]_p4 smii mode lnkact_p4, smii_txd_p 4 ss_smii mode lnkact_p4, sssmii_txd_p4 i, ttl, pd port 4 rmii tran smit data. transmit data for port 4 in puts the di-bit s that re tran smitted a nd are driven synchrono usl y to refclk. no te that in 100mb/s mod e , txd ca n ch an ge on ce per refclk cycle, whe r ea s in 10m b/s mode, txd must be held ste ady for 10 con s e c utive refcl k cycle s . link a nd acti vity led / port 4 smii transmit data. txd0 for port 4 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to smii_refclk (pi n 70 ). in 100mb/s mode, txd0 inputs a new 1 0 -bit se gment sta r tin g with sync. in 10mb/s mode, txd0 mu st repeat ea ch 1 0 -bit segme n t 10 times. txd1_p 4 act s as po rt 4 link/activity led in both smii and ss_smii mode. see led description f o r mo re detail . link a nd acti vity led/port 4 ss_smii transmit data. txd0 for port 4 inp u ts the data that is tran smitted and is d r iven synchrono usl y to txclk (pin 70 ). in 100mb/s mo de, txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 78 rmii mode txen_p4 smii mode smii_refclk i, ttl port 4 tran smit enable. tran smit ena b le for po rt 4 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refc lk. smii 125m refere nce clo ck. in smii mode, this pin acts a s 125m referen c e cl ock for al l ports. all transmit an d re ceive data (in c lud e tran smit enable a n d re ceive dat a valid) shoul d be synchrono us to the risin g e dge of this cl ock.
ADM7008 interf ace description pin # pin name ty p e pin descrip tion admtek inc. 2-10 ss_smii mode txclk ss_smii 125m tran smit clock. in ss_ smii mode, this pin a c ts as 12 5m tran smit clo c k for all port s . txd and txe n sho u ld be synchrono us to the risin g e dge of this cl ock. 81, 82 power on setting rec_10m _p 3, anendis rmii mode rxd[1:0]_p3 smii mode spdled_p3, smii_rxd_p 3 ss_smii mode spdled_p3, sssmii_rxd_p 3 i/o, 8ma, pd rec_10m: value on rxd1_p3 will b e latche d by adm700 8 duri ng po we r on re set a s port 3 10m re-comm and val ue. 0: recomme nd port 3 to operate in 100 m mode 1: recomme nd port 3 to operate in 10m mode twi s ted pair dupl ex re co mmend val u e. value on rxd1 will be latch ed by adm700 8 du ring p o wer on reset as auto negotiatio n di sabl e re com m end valu e for twi s ted pai r interfa c e. 0: auto-neg otiation enabl e for all twiste d pair p o rts. 1: auto-neg otiation di sabl e for all twisted pair po rts port 3 rmii rec e ive data. rxd[ 1:0] are the port 3 out put di- bits syn c h r on ously to ref c lk. upo n a s sertio n of crsdv_p, rxd0 and rxd1 re main a t 00 until valid data is outpu t from the fifo onto rxd. the start of valid data is indicated b y 01 on rxd1 and rxd0. if a false ca rrie r or a symbol e r ror i s detecte d, rx d1 an d rx d0 are set to 10 for the dura t ion of the activity. note that in 100m b/s mod e rx d ca n ch ang e once pe r refclk cycl e, whe r ea s in 10mb/s mo d e rxd mu st be held steady for 1 0 con s e c ut ive refclk cycl es. port 3 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to smii refclk (pin 70 ). in 100mb/s mode, rxd0 output s a ne w 10 -bi t segme n t sta r ting with sy nc. in 10mb/ s mode , rxd0 mu st rep eat ea ch 1 0 bits se gme n t 10 times. rxd1 for the de sign ated po rt is a c ted a s spee d status led for po rt 3. port 3 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 3. 83 power on setting testsel2 rmii mode crs dv_p3 i, pd o, 8ma indust r ial te st mode select 2. value on this pin will b e latche d by adm700 8 duri ng po we r on re set a s in dust r ial test mode sele ct bit 2. pull down for norm a l ope ra tion. for test mode, see test sel e ct 0 for more detail port 3 ca rrie r sense/ re cei v e data valid . crsdv_p3 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p3 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p3 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv_p3 i s asse rted synch r o nou sly to refclk. the toggling of crsdv_p 3 on the first and se con d di-bit contin ue s til l l t h d t i th fifo i t d t rx d
ADM7008 interf ace description pin # pin name ty p e pin descrip tion admtek inc. 2-11 smii mode n/a ss_smii mode rx_syn c until all the data in the fifo is presente d onto rx d. crs dv_p3 i s asse rted for the durat io n of carrie r acti vity for a fals e carrier event. not used. not used in s m ii mode ss_smii receive synchro n izatio n sign al. in ss_smii mode, this pin sets the bit s t ream alignment of sss_smii_rxd for all port s . 84, 85 rmii mode txd[1:0]_p3 smii mode lnkact_p3, smii_txd_p 3 ss_smii mode lnkact_p3, sssmii_txd_p3 i, ttl, pd port 3 rmii tran smit data. transmit data for port 3 in puts the di-bit s that re tran smitted a nd are driven synchrono usl y to refclk. no te that in 100mb/s mod e , txd ca n ch an ge on ce per refclk cycle, whe r ea s in 10m b/s mode, txd must be held ste ady for 10 con s e c utive refcl k cycle s . link a nd acti vity led/port 3 sm ii transmit data. txd0 for port 3 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to smii_refclk (pi n 70 ). in 100mb/s mode, txd0 inputs a new 1 0 -bit se gment sta r tin g with sync. in 10mb/s mode, txd0 mu st repeat ea ch 1 0 -bit segme n t 10 times. txd1_p 3 act s as po rt 3 link/activity led in both smii and ss_smii mode. see led description f o r mo re detail . link a nd acti vity led/port 3 ss_smii transmit data. txd0 for port 3 inp u ts the data that is tran smitted and is d r iven synchrono usl y to txclk (pin 70 ). in 100mb/s mo de, txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 86 rmii mode txen_p3 smii mode smii_sync ss_smii mode tx_sync i, ttl port 3 tran smit enable. tran smit ena b le for po rt 3 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refc lk. smii synchro n izatio n sign al. in sm ii mode, this pin sets the bit stre am align m ent of smii_txd an d smii_rxd for all port s . ss_smii transmit synch r onization sig nal. in ss_smii mode, this pin sets the bit s t ream alignment of sss_smii_txd for all port s . 89, 90 power on setting rec_10m _p 2, phyaddr0 rmii mode rxd[1:0]_p2 i, pd, pd o, 8ma rec_10m: value on rxd1_p2 will b e latche d by adm700 8 duri ng po we r on re set a s port 2 10m re-comm and val ue. 0: recomme nd port 2 to operate in 100 m mode (100 m) 1: recomme nd port 2 to operate in 10m mode phy address bit 0. value on rx d1 will be latched by adm70 08 du ring p o wer on reset as phy addre s s bit 0. com b ine d wit h phyad dr 1 (pin 44) to form phy addres s for adm70 08. see phyaddr1 de scri ptio n for more de tail port 2 rmii rec e ive data. rxd[ 1:0] are the port 2 out put di- bits syn c h r on ously to ref c lk. upo n a s sertio n of crsdv_p, rxd0 and rxd1 re main a t 00 until valid data is outpu t from the fifo t r xd th t t f lid d t i i di t d b 0 1
ADM7008 interf ace description pin # pin name ty p e pin descrip tion admtek inc. 2-12 smii mode spdled_p2, smii_rxd_p 2 ss_smii mode spdled_p2, sssmii_rxd_p 2 fifo onto rxd. the start of valid data is indicated b y 01 on rxd1 and rxd0. if a false ca rrie r or a symbol e r ror i s detecte d, rx d1 an d rx d0 are set to 10 for the dura t ion of the activity. note that in 100m b/s mod e rx d ca n ch ang e once pe r refclk cycl e, whe r ea s in 10mb/s mo d e rxd mu st be held steady for 1 0 con s e c ut ive refclk cycl es. port 2 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to smii refclk (pin 70 ). in 100mb/s mode, rxd0 output s a ne w 10 -bi t segme n t sta r ting with sy nc. in 10mb/ s mode , rxd0 mu st rep eat ea ch 1 0 bits se gme n t 10 times. rxd1 for the de sign ated po rt is a c ted a s spee d status led for po rt 2. port 2 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 2. 91 power on setting fx_duplex rmii mode crs dv_p2 smii/ss_smi i mode n/a i/o, 8ma pu dupl ex re co mmend val u e for fibe r port. value on this pin will be latch ed by adm700 8 du ring p o wer on reset as du pl ex re comm end v a lue for all fib e r po rts. 0: half duplex for all fiber p o rts. 1: full duplex for all fiber p o rts. port 2 ca rrie r sense/ re cei v e data valid . crsdv_p2 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p2 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p2 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv_p2 i s asse rted synch r o nou sly to refclk. the toggling of crsdv_p 2 on the first and se con d di-bit contin ue s until all the data in the fifo is presente d onto rx d. crs dv_p2 i s asse rted for the durat io n of carrie r acti vity for a fals e carrier event. not used. not used in s m ii and ss_smii mode 92, 93 rmii mode txd[1:0]_p2 smii mode lnkact_p2, smii_txd_p 2 i, ttl, pd port 2 rmii tran smit data. transmit data for port 2 in puts the di-bit s that re tran smitted a nd are driven synchrono usl y to refclk. no te that in 100mb/s mod e , txd ca n ch an ge on ce per refclk cycle, whe r ea s in 10m b/s mode, txd must be held ste ady for 10 con s e c utive refcl k cycle s . link a nd acti vity led/port 2 sm ii transmit data. txd0 for port 2 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to smii_refclk (pi n 70 ). in 100mb/s mode, txd0 inputs a new 1 0 bit s e g men t s ta rtin g w ith sync i n 10mb/s m ode
ADM7008 interf ace description pin # pin name ty p e pin descrip tion admtek inc. 2-13 ss_smii mode lnkact_p2, sssmii_txd_p2 new 1 0 -bit se gment sta r tin g with sync. in 10mb/s mode, txd0 mu st repeat ea ch 1 0 -bit segme n t 10 times. txd1_p 2 act s as po rt 2 link/activity led in both smii and ss_smii mode. see led description f o r mo re detail . link a nd acti vity led/port 2 ss_smii transmit data. txd0 for port 2 inp u ts the data that is tran smitted and is d r iven synchrono usl y to txclk (pin 70 ). in 100mb/s mo de, txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 94 rmii mode txen_p2 smii/ss_smi i low i, ttl port 2 tran smit enable. tran smit ena b le for po rt 2 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refc lk. not used. ti ed to low fo r normal op eration in smii/ss_smii mode. 95, 96 power on setting rec_10m _p 1, testsel1 rmii mode rxd[1:0]_p1 smii mode spdled_p1, smii_rxd_p 1 ss_smii mode spdled_p1, sssmii_rxd_p 1 i/o, 8ma, pd rec_10m: value on rxd1_p1 will b e latche d by adm700 8 duri ng po we r on re set a s port 1 10m re-comm and val ue. 0: recomme nd port 1 to operate in 100 m mode 1: recomme nd port 1 to operate in 10m mode indust r ial te st mode select 1. value on rxd0_p1 will be latche d by adm7 008 d u ri ng po we r on reset a s indu strial test mode sele ct bit 1. pull down for n o rm al operation. for te st mode, see te st sele ct 0 for more detail port 1 rmii rec e ive data. rxd[ 1:0] are the port 1 out put di- bits syn c h r on ously to ref c lk. upo n a s sertio n of crsdv_p, rxd0 and rxd1 re main a t 00 until valid data is outpu t from the fifo onto rxd. the start of valid data is indicated b y 01 on rxd1 and rxd0. if a false ca rrie r or a symbol e r ror i s detecte d, rx d1 an d rx d0 are set to 10 for the dura t ion of the activity. note that in 100m b/s mod e rx d ca n ch ang e once pe r refclk cycl e, whe r ea s in 10mb/s mo d e rxd mu st be held steady for 1 0 con s e c ut ive refclk cycl es. port 1 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to smii refclk (pin 70 ). in 100mb/s mode, rxd0 output s a ne w 10 -bi t segme n t sta r ting with sy nc. in 10mb/ s mode , rxd0 mu st rep eat ea ch 1 0 bits se gme n t 10 times. rxd1 for the de sign ated po rt is a c ted a s spee d status led for po rt 1. port 1 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 1. 97 power on i/o, fiber/twis t ed pair confi g uration bit 1. value on rxd1 will be
ADM7008 interf ace description pin # pin name ty p e pin descrip tion admtek inc. 2-14 setting selfx1 rmii mode crs dv_p1 smii/ss_smi i mode n/a 8ma pd latche d by adm7 008 d u ri ng po we r on reset a s fiber/t wiste d pai r interfa c e conf iguration bit 1 . combine d with selfx0 (power on setting val ue on rx d0 _ p 0) to pro g ra m adm70 08 i n to 4 different mod e s. 00: all port s a r e twi s ted po rts 01: only port 7 is fiber p o rt, and all the other p o rts a r e twisted port s . 10: only port 7 and po rt 6 are fibe r po rts, and all the other p o rt are twi s ted port 11: all port s a r e fiber p o rt s. port 1 ca rrie r sense/ re cei v e data valid . crsdv_p1 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p1 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p1 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv_p1 i s asse rted synch r o nou sly to refclk. the toggling of crsdv_p 1 on the first and se con d di-bit contin ue s until all the data in the fifo is presente d onto rx d. crs dv_p1 i s asse rted for the durat io n of carrie r acti vity for a fals e carrier event. not used. not used in s m ii and ss_smii mode 98, 99 rmii mode txd[1:0]_p1 smii mode lnkact_p1, smii_txd_p 1 ss_smii mode lnkact_p1, sssmii_txd_p1 i, ttl, pd port 1 rmii tran smit data. transmit data for port 1 in puts the di-bit s that re tran smitted a nd are driven synchrono usl y to refclk. no te that in 100mb/s mod e , txd ca n ch an ge on ce per refclk cycle, whe r ea s in 10m b/s mode, txd must be held ste ady for 10 con s e c utive refcl k cycle s . link a nd acti vity led/port 1 sm ii transmit data. txd0 for port 1 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to smii_refclk (pi n 70 ). in 100mb/s mode, txd0 inputs a new 1 0 -bit se gment sta r tin g with sync. in 10mb/s mode, txd0 mu st repeat ea ch 1 0 -bit segme n t 10 times. txd1_p 1 act s as po rt 1 link/activity led in both smii and ss_smii mode. see led description f o r mo re detail . link a nd acti vity led/port 1 ss_smii transmit data. txd0 for port 1 inp u ts the data that is tran smitted and is d r iven synchrono usl y to txclk (pin 70 ). in 100mb/s mo de, txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 100 rmii mode txen_p1 smii/ss_smi i low i, ttl port 1 tran smit enable. tran smit ena b le for po rt 1 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refc lk. not used. ti ed to low fo r normal op eration in smii/ss_smii mode.
ADM7008 interf ace description pin # pin name ty p e pin descrip tion admtek inc. 2-15 105, 106 power on setting rec_10m _p 0, testsel0 rmii mode rxd[1:0]_p0 smii mode spdled_p0, smii_rxd_p 0 ss_smii mode spdled_p0, sssmii_rxd_p 0 i/o, 8ma, pd rec_10m: value on rxd1_p0 will b e latche d by adm700 8 duri ng po we r on re set a s port 0 10m re-comm and val ue. 0: recomme nd port 0 to operate in 100 m mode 1: recomme nd port 0 to operate in 10m mode indust r ial te st mode select 0. value on rxd0_p1 will be latche d by adm7 008 d u ri ng po we r on reset a s indu strial test mode sele ct bit 0. pull down testsel [2:0] for norm a l ope ration. testsel mode 000: no rmal mode port 0 rmii rec e ive data. rxd[ 1:0] are the port 0 out put di- bits syn c h r on ously to ref c lk. upo n a s sertio n of crsdv_p, rxd0 and rxd1 re main a t 00 until valid data is outpu t from the fifo onto rxd. the start of valid data is indicated b y 01 on rxd1 and rxd0. if a false ca rrie r or a symbol e r ror i s detecte d, rx d1 an d rx d0 are set to 10 for the dura t ion of the activity. note that in 100m b/s mod e rx d ca n ch ang e once pe r refclk cycl e, whe r ea s in 10mb/s mo d e rxd mu st be held steady for 1 0 con s e c ut ive refclk cycl es. port 0 smii receive data. rxd0 for the desi gnate d p o rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to smii refclk (pin 70 ). in 100mb/s mode, rxd0 output s a ne w 10 -bi t segme n t sta r ting with sy nc. in 10mb/ s mode , rxd0 mu st rep eat ea ch 1 0 bits se gme n t 10 times. rxd1 for the de sign ated po rt is a c ted a s spee d status led for po rt 0. port 0 ss_smii receive data. rxd0 for the de sign ated po rt outputs d a ta or in-ban d m anag eme n t information synchrono usl y to rxclk (pin 75 ). in 100mb/s mo de, rxd0 outputs a n e w 10 -bit se g m ent startin g with sync. in 10mb/ s mode, rx d0 must re peat e a ch 1 0 bits segme n t 10 times. rxd1 for the desi gnate d p o rt is a c ted a s spee d status le d for port 0. 107 power on setting selfx0 rmii mode crs dv_p0 i/o, 8ma pd fiber/t wi sted pair configurati on bit 0. value on rxd1 will be latche d by adm7 008 d u ri ng po we r on reset a s fiber/t wiste d pai r interfa c e conf iguration bit 1 . combine d with selfx1 (power on setting val ue on rx d0 _ p 1) to pro g ra m adm70 08 i n to 4 different mod e s. see selfx1 for more detail port 0 ca rrie r sense/ re cei v e data valid . crsdv_p0 assert s whe n the re ceive medium is non -idl e. the asse rtion of crs dv_p0 i s asyn ch ro no us to ref c l k . at the de-asse rtion of carrie r, crsdv_p0 de -a ssert s syn c hronou sly to refclk only on the first di-bit of rx d. if there is still data in the fifo not yet prese n ted onto rx d, then on th e se con d di-b it of rxd, crs dv_p0 i s asse rted synch r o nou sly to refclk. the toggling of crsdv_p 0 on the first and se con d di-bit contin ue s until all the data in the fifo is presente d onto rx d. crs dv p0 i t d f th d t i f i t i i t f
ADM7008 interf ace description pin # pin name ty p e pin descrip tion smii/ss_smi i mode n/a crs dv_p0 i s asse rted for the durat io n of carrie r acti vity for a fals e carrier event. not used. not used in s m ii and ss_smii mode 108, 109 rmii mode txd[1:0]_p0 smii mode lnkact_p0, smii_txd_p 0 ss_smii mode lnkact_p0, sssmii_txd_p0 i, ttl, pd port 0 rmii tran smit data. transmit data for port 1 in puts the di-bit s that re tran smitted a nd are driven synchrono usl y to refclk. no te that in 100mb/s mod e , txd ca n ch an ge on ce per refclk cycle, whe r ea s in 10m b/s mode, txd must be held ste ady for 10 con s e c utive refcl k cycle s . link a nd acti vity led/port 0 sm ii transmit data. txd0 for port 0 inputs the d a ta that is tra n smitted a nd is drive n syn c hro nou sly to smii_refclk (pi n 70 ). in 100mb/s mode, txd0 inputs a new 1 0 -bit se gment sta r tin g with sync. in 10mb/s mode, txd0 mu st repeat ea ch 1 0 -bit segme n t 10 times. txd1_p 0 act s as po rt 0 link/activity led in both smii and ss_smii mode. see led description f o r mo re detail . link a nd acti vity led/port 0 ss_smii transmit data. txd0 for port 1 inp u ts the data that is tran smitted and is d r iven synchrono usl y to txclk (pin 70 ). in 100mb/s mo de, txd0 inputs a n e w 10-bit segm e n t starting with sync. in 10mb/s mode, txd0 must re peat e a ch 1 0 -bit se gment 10 tim e s. 110 rmii mode txen_p0 smii/ss_smi i low i, ttl port 0 tran smit enable. tran smit ena b le for po rt 0 indicates that the di-bit on txd is val i d and it is dri v en synchron ously to refc lk. not used. ti ed to low fo r normal op eration in smii/ss_smii mode. 2.2.7 atpg signals, 2 pins pin # pin name ty p e des c ription 1 1 4 s c a n _ e n i vlttl scan_e n: scan e nabl e for test 0: norm al mode 1 1 3 s c a n _ m o d e i vlttl scan_ m o d e: scan mod e sele ct for te st 0: norm al mode 2.2.8 reset pin pin # pin name ty p e des c ription 4 7 r e s e t # i , sche re set signal. active low to brin g adm7 008 into reset con d ition. re comm end ke eping lo w for at least 200 ms to ensure the st ability of the sy stem after power on reset. 2.2.9 control signals, 3 pins admtek inc. 2-16 pin # pin name ty p e pin descrip tion 1 0 1 m d i o i / o , lvttl mana geme n t data. mdio tran sfers ma n agem ent data in and out of the device syn c h r o n ous to m dc. 1 0 2 m d c i , lvttl mana geme n t data referen c e cl ock. a non -continu o u s cl ock input for man agem ent usa ge. adm700 8 will use this clock to sam p le data i n p ut on m d io and d r ive d a ta onto mdi o
ADM7008 interf ace description acco rdin g to rising e dge of this clo c k. 4 4 p h y a d d r 1 i , lvttl phy addre ss bit 1. pure input of adm7 008. com b in ed with phyaddr0 to form the m o st significan t 2 bits of phy addre s s for ADM7008. the lsb 3 bits will be assigned by ADM7008 automati c ally acco rdin g to port num be r 000 port 0 001 port 1 010 port 2 011 port 3 100 port 4 101 port 5 110 port 6 111 port 7 2.2.10 led interface, 2 pins pin # pin name t y pe description 5 0 l e d _ c l k i/o, 4ma, pd led cl ock. non - contin u ous cloc k for serial output led status. the clock high d u ration is 40 n s and low fo r 6 00n s. this 6 40 n s p e rio d form s o ne clo c k cycl e and 24 clo c ks fo rm one le d burst. the first clock output is use d to latch the first bit on led_ data (see led_ data for more d e tail) a nd the final clo ck i s use d to latch the last data on led_dat a . led_ clk will be kept lo w for 40 m s befo r e next led stream data is outp u t. 4 9 l e d _ d a t a i/o, 4ma, pd led data. 8 port status o u tput with differe nce se que nce acco rdin g to different interf ace. data _l ed is drive n out by adm70 08 at the falling ed g e of clk_le d. system desig n sho u ld u s e th e risi ng ed ge of led_ clk to latch the da ta on led_ data. the outp u t se quen ce i s : dup co l0 (f irst bit output) ? du pc ol1 ? ? ? du pcol 7 ? speed0 ? speed1 ? ? ? speed7 ? lnkact0 ? lnkact1 ? ? ? lnkact7 (las t bit output) 2.2.11 regulator control, 2 pins pin # pin name ty p e des c ription 1 1 7 c o nt r o l o , analog reg u lato r co ntrol. voltage control to external 1.8v reg u lat o r. see 4.2.9 for more function d e scription. 1 1 9 r t x i , analog con s tant volt age referen c e. external 1.1k ? 1% re sisto r con n e c tion to grou nd. 2.2.12 digital pow er/ground, 13 pins admtek inc. 2-17 pin # pin name ty p e pin descrip tion 58, 80 104 gn d o d i g i t a l gro und gro und u s e d by 3.3v i/o. 46, 72, 88, 112 gn d i k d i g i t a l gro und gro und u s e d by core. 57, 79 vcc3o di g ital 3.3v powe r u s ed by i/o
ADM7008 interf ace description admtek inc. 2-18 1 0 3 p o w e r 45, 71, 87 v c c 2 i k d i g i t a l power 1.8v powe r u s ed by core
ADM7008 function description chapter 3 function description ADM7008 integrates eight 100base-x physical sublayer (phy), 100base-tx physical m e dium dependent (pmd) transceivers, eight co mplete 10base-t m odules into a single chip for both 10 mbits/s and 100 mbits/s e t hernet operation. it also supports 100base - fx operation through external fiber-optic transceivers. the device is capable of operating in either full-duplex m o de or ha lf-duplex m ode in either 10 mbits/s or 100 mbits /s ope ration. ope r ation a l m odes can be selected by hardware configuration pins, software settings of m a nagem e nt registers, or determ ined by the on-chip auto negotiation logic. the 10base-t section of the device consists of the 10 mbits/s tr ansceiver m odule with f ilters and a manchester endec m o dule. figure 3-1 adm7 008 s w i t ch applica t ion (10/1 00m tp mode) ADM7008 consists of eight kinds of m a jor blocks: x eight 10/100m phy bl ocks x mac interface x led display x smi admtek inc. 3-1 ad m 7008 50 / 1 2 5 m h z r m ii/ s m ii[ 0 ] r m ii/ s m i i [ 1 ] r mii/ s m ii[ 2 ] rm i i / s m ii[ 3 ] r m ii/ s m ii[ 4 ] r m ii/ s m ii[ 5 ] r m ii/ s m ii[ 6 ] rmii/ s m ii[ 7 ] t xp[ 0 ] / t xn [ 0 ] r xp[ 0 ] / r xn [ 0 ] t xp[ 0 ] / t xn [ 0 ] r xp[ 0 ] / r xn [ 0 ] t xp[ 0 ] / t xn [ 0 ] r xp[ 0 ] / r xn [ 0 ] t xp[ 0 ] / t xn [ 0 ] r xp[ 0 ] / r xn [ 0 ] t xp[ 0 ] / t xn [ 0 ] r xp[ 0 ] / r xn [ 0 ] t xp[ 0 ] / t xn [ 0 ] r xp[ 0 ] / r xn [ 0 ] t xp[ 0 ] / t xn [ 0 ] r xp[ 0 ] / r xn [ 0 ] t xp[ 0 ] / t xn [ 0 ] r xp[ 0 ] / r xn [ 0 ] re f c l k ma c ma c ma c ma c ma c ma c ma c ma c sw it c h f a b r ic rj - 4 5 ma g n e t i c s ma g n e t i c s rj - 4 5 rj -4 5 rj - 4 5 rj - 4 5 rj - 4 5 rj - 4 5 rj -4 5
ADM7008 function description x power managem e nt x clock generator x voltage reg u lator each 10/100m phy block contains: x 10m phy block x 100m phy block x auto-negotiation x cable broken detector x other digital control blocks 3.1 10/100m phy block the 100base-x section of the device im pl e m ents he following functional blocks : x 100base-x physical coding sub-layer (pcs) x 100base-x physical m e dium attachm e nt (pma) x twisted-pa ir pmd (tp-pmd) trans c e i ver the 100base-x and 10base-t sections sh are the following functional blocks : x clock synthesizer m odule x mii regis t e r s x ieee 802.3u auto negotiation the interfaces used for comm unication be tween phy block and switch core is mii interface. 3.1.1 100base-x module ADM7008 imple m ents 100base-x com p liant pcs and pma and 100base-tx compliant tp-pmd as illus t ra ted in figure 4. bypass options f o r e ach of the m a jor f unctional blocks within the 100base-x pcs provides fl exibility for various applications. 100 mbps phy loop back is included for diagnostic purpose. 3.1.2 100base-tx receiver for 100base-tx operation, the on-chip twisted pair receiver that consists of a differential line receiver, an adaptiv e equa lizer and a base-line wander co m p ensation circuits detects the incom i ng signal. ADM7008 uses an adaptive equalizer that changes filter frequency response in accordance with cable length. the cable length is estim ated based on the incom i ng signal strength. the equalizer tunes itself autom a tically for any ca ble length to com p ensate f o r the am plitude and phase distor tions incurred fro m the cable. admtek inc. 3-2 the 100base-x receiver consists of functional blocks require d to recover and condition the 125 mbps receive data stream . the ADM7008 im ple m ents the 100base-x receiving state m achine diagram as given in ans i/ieee standard 802.3u, clause 24. the 125 mbps receive data stream m a y originate from the on-chip twisted-pa ir transc eive r in a
ADM7008 function description 100base-tx application. alte rnatively, the receive data st ream m a y be generated by an external optical receiver as in a 100b ase-fx application. the receiv e r block consists of the following functional sub - blocks : x a/d converter x adaptive equalizer and tim i ng rec overy module x nrzi/nrz and seria l/p arallel deco der x descram b ler x sym bol alignm ent block x sym bol decoder x collision de tect block x carrier sense block x stream dec oder block a/d converter high perform a nce a/d converter with 125m sampling rate converts sig n als receiv e d on rxp/rxn pins to 6 bits data stream s ; besides it possess auto -gain-contro l cap ability that will furthe r im prove receiv e pe rfor m ance especia lly u nder long cable o r h a rsh detrim ental signal in tegr ity. due to high pass characteristic on transf or m e r, built in base- line-wande r correc ting c i rcuit will c a n cel it out and restore its dc level. figure 3-2 1 00base -x bl ock diag ram and da ta pa th adaptive equalizer and timing recovery module all digital design is especial immune fr om noise environm ents and achieves better admtek inc. 3-3 m ii to s m ii c o n v e r t e r rx d 4b / 5 b d e c ode r de s c r a m b l e r s e ri a l - t o- p a r a l l el c l oc k/ da ta re c o v e ry a d a ptive eq u a l i ze r s m ii to m ii c o n v e r te r rx st a t e ma c h i n e sy n c r x d [ 3: 0] rx p rx n sd p bp _ d s c r cr s rx dv rx e r 1 0 0 b a s e - x re ce iv e r tx st a t e ma ch i n e 4b / 5 b dec ode r scr a m b l e r p a r a llal- t o - s e r i a l mlt - 3 st a t e mac h i n e 10/ 100 tx driver fi be r op t i c driver sy n c tx d co l tx c l k tx e n tx e r tx d [ 3 : 0 ] bp _ s c r tx p tx n tx p tx n 100b a s e - x t r a n s m i t t e r a/d b l o c k te s t m d nr zi t o 6 b nr z to nr z i fi b e r o p t i c r ece i v er rx p rx n
ADM7008 function description correlations between pr oduction and system testing. baud rate adaptive equalizer/tim ing recovery com p ensates line lo ss induced f r om twisted pair and tr acks far end clock at 125m sam p les per second. adaptive equalizer im plem e n ted with f eed forward and decision f eedback techniques m eet the requ ire m ent of ber less than 10-12 for transm ission on cat5 twisted pair cable ranging from 0 to 140 m e ters. nrzi/nrz and serial/parallel decoder the recovered data is converted from nrzi to nrz. the data is not n e cessa rily a l igned to 4b/5b code group?s boundary. data descrambling the descrambler acquires synchronization with the data stream by r ecognizing idle bursts of 40 or m o re bits and locki ng its deciphering linear feedb ack shif t r e giste r (lfsr) to the state of the scram b ling lfsr. upon ach ieving synchronization, th e incom i ng data is xored by t h e deciphering lfsr and descram b led. in order to m a intain synchr onization, the descram b ler continuously m o nitors the validity of the unscram bled data that it gen e rates. to en sure th is , a link state m o nitor and a hold tim er are used to constantly m onitor the s ynchronization status. upon synchronization of the descrambler the hold tim er starts a 722 us countdown. upon detection of at least 6 idle sym bols (30 consecutive ?1?) w ithin the 722 us period, the hold timer will reset and begin a new countdown. this m oni toring opera tion will co ntinue indef i nitely given a properly operating network connection with good signal integrity. if the link state monitor does not recognize at least 6 unscram bl ed idle sym b ols within 722 us period, the descram b ler will be f o rced out of the current s t ate of synchronization and reset in o r d e r to re-acquire synchronization. symbol alig nment the sym bol alignm ent circuit in the adm 7008 determ ines code word alignm ent by recognizing the /j/k delim iter pair. this circuit operates on unaligned data from the descram b ler. once the /j/k sym bol pair ( 11000 10001) is detected, subsequent data is aligned on a fixed boundary. symbol decoding admtek inc. 3-4 the sym bol decoder functions as a look-up ta ble that translates incom i ng 5b symbols into 4b nibbles as shown in table 3-1. the symbol decoder first de te cts the /j/k symbol pair p r eced ed by idle sym bols and replaces the sym bol with mac pream ble. all subsequent 5b sym bols are converted to the corresponding 4b nibbles for the duration of the en tire p acket. this conversion ceases upo n the d e tection of the /t/r sym bol pair denoting the end of stream deli m iter (esd). the trans l ated data is p r esented on the intern al rxd[ 3:0] signal line s with rxd[ 0] represen ts th e least s i gnif i cant bit of the trans l ated n i bble.
ADM7008 function description pcs code-gro up [4 : 0 ] na me mii (txd/r xd) <3:0> interpretation 1111 0 0 0 0 0 0 d a t a 0 0100 1 1 0 0 0 1 d a t a 1 1010 0 2 0 0 1 0 d a t a 2 1010 1 3 0 0 1 1 d a t a 3 0101 0 4 0 1 0 0 d a t a 4 0101 1 5 0 1 0 1 d a t a 5 0111 0 6 0 1 1 0 d a t a 6 0111 1 7 0 1 1 1 d a t a 7 1001 0 8 1 0 0 0 d a t a 8 1001 1 9 1 0 0 1 d a t a 9 1011 0 a 1 0 1 0 d a t a a 1011 1 b 1 0 1 1 d a t a b 1101 0 c 1 1 0 0 d a t a c 1101 1 d 1 1 0 1 d a t a d 1110 0 e 1 1 1 0 d a t a e 1110 1 f 1 1 1 1 d a t a f 1111 1 i u n d e f i n e d i d l e used as inter-stream fill code 1100 0 j 0101 start-of-stream delimiter, part 1 of 2; alway s used in pairs with k 1000 1 k 0101 start-of-stream delimiter, part 2 of 2; alway s used in pairs with j 0110 1 t u n d e f i n e d start-of-strea m delimiter, part 1 of 2; alway s used in pairs with r 0 1 1 1 r u n d e f i n e d start-of-stream delimiter, part 2 of 2; alway s used in pairs with t 0010 0 h u n d e f i n e d transm i t e r r o r ; used to force signaling errors 0000 0 v u n d e f i n e d i n v a l i d c o d e 0000 1 v u n d e f i n e d i n v a l i d c o d e 0001 0 v u n d e f i n e d i n v a l i d c o d e 0001 1 v u n d e f i n e d i n v a l i d c o d e 0010 1 v u n d e f i n e d i n v a l i d c o d e 0011 0 v u n d e f i n e d i n v a l i d c o d e 0100 0 v u n d e f i n e d i n v a l i d c o d e 0110 0 v u n d e f i n e d i n v a l i d c o d e 1000 0 v u n d e f i n e d i n v a l i d c o d e 1100 1 v u n d e f i n e d i n v a l i d c o d e admtek inc. 3-5 table 3-1 lo ok-up t a ble for tr ansla t ing 5b sy mbols into 4b nibbles.
ADM7008 function description valid data signal the valid d a ta s i gnal ( r xdv) indicate s tha t recovered and decoded nibbles are being presented on the internal rxd[3:0] sync hronous to receive clock, rxclk. rxdv is asserted when the first n i bble of tran slated /j/k is ready for transfer over the inte rnal mii. it r e m a ins active un til either th e /t /r delim iter is recogn ized , link test indicates failure, or no signal is detected. on any of th ese conditions, rxdv is deasserted. receive err o rs the rxer signal is used to comm unicate receiv er erro r con d itions. w h ile the receiver is in a state of holding rxdv asserted, the rxer will be asserted for ea ch code word that does not m a p to a valid code-group. 100base-x link monitor the 100base-x link m o nitor functio n allows the receiv e r to ensure th at reliable data is being receiv ed. w ithout reliab l e data recep tion, the link m onitor will halt both transm i t and rece ive operations u n til su ch tim e that a v a lid link is d e tected. the ADM7008 performs the link integrity test as outlined in ieee 100ba s e-x (clause 24) link m onitor sta t e d i agr a m. the link sta t us is m u ltip lexed w ith 10 mbits / s link s t a t u s to for m the reportable link status bit in serial m a nagem e nt register 1h, and driven to the lnkact pi n. when persistent signal energy is detected on th e network, the logic m oves into a link- ready state after approxim ately 500 us, and wait s for an enable from the auto negotiation module. when receive, the link-up state is entered, and the transm ission and reception logic blocks becom e active. should auto nego tiation be disabled, th e link integrity logic moves immediately to the link-up state after entering th e lin k-ready s t ate. carrier sen s e carrier sense (crs) for 100 mbits/s operatio n is asserted upon th e detection of two noncontiguous zeros occurring within any 10-b it boundary of the received data stream . the carrier sense function is i ndependent of symbol alignm ent. in switch m ode, crs is asserted during either packet transm ission or reception. for rep eater m ode, crs is asserted on ly during packet recep tion. w h en the id le sy mbol pair is detected in the receiv e d data stream , crs is deasserted. in repeater m ode, crs is only asserted d u e to receiv e activ ity. crs is in tended to encapsulate rxdv. bad ssd detection a bad start of stream delim iter (b ad ssd) is an error c ondition th a t occurs in the 100base-x receiv e r if carrier is detected (crs asserted ) a nd a valid /j/k set of code- group (ssd) is not received. admtek inc. 3-6 if this cond ition is detected, then the ADM7008 will as sert rxer and present rxd[3:0] = 1110 to the internal mii for the cycles ha t correspond to received 5b code-groups until
ADM7008 function description at least two idle code-groups are detected. once at least two idle code groups are detected, rxer and crs becom e deasserted. far-end fa ult auto negotiation provides a m echa n ism for transferring infor m ation from the local station to the link partner that a rem o te fault has occurred for 100base-tx. as auto negotiation is not currently specified for opera tion over fiber, the fa r end f a ult ind i ca tion function (fefi) provides this capabi lity for 100base-fx applications. a rem o te f a ult is an err o r in the lin k that one s t ation can d e tect while the other can not. an exam ple of this is a disconnected wire at a s t ation ? s tran sm itter. th is station will be receiv i ng valid data and detect th at the link is good via the link integrity monitor, but will not be able to detect that its transm i ssion is not propagating to the other station. a 100base-fx station that detects such a re m o te fault m a y m odify its transm itted idle stream from all ones to a gr oup of 84 ones followed by a single 0. this is referred to as the fefi idle patte rn. the fefi function is controlled by bit 3 of register 11h. it is initialized to 1 (encoded) if the selfx pin is at logic high level during power on reset. if the fefi function is enabled the ADM7008 will halt al l curren t operations and tran sm it the f e fi idle pattern when fosd signal is de-asserted following a good link indication from the link integrity monitor. f o sd signal is gene rate d inte rnally f r om the interna l sign al detect cir c uit. transm ission of the fefi idle patte r n will c ontinue until link up signal is asse rted . if three or m o re fefi idle patterns are detect ed by the ADM7008, then bit 4 of the basic mode status regis t er (ad d ress 1h ) is set to on e u n til read by m a na gem e nt. additiona lly, upon detection of far end fault, all receive and transm it mii activity is disabled/ignored. 3.1.3 100base-tx transmitter ADM7008 imple m ents a tp-pmd com p liant tr ansceiver for 100base-tx operation. the dif f e rential transm it driv er is sha r ed by the 10base-t and 100base-tx subsystem s . this arrangem e nt results in one device that uses the sam e external m a gnetics for both the 10base-t and the 100base-tx transm ission with sim p le rc com p onent connections. the individually wave-shaped 10base-t and 100base-tx transm it signals are multiplexed in the trans m issi on output driver selection. ADM7008 100base-tx transm ission driver im plem ents mlt-3 translation and wave- shaping functions. the rise/fall tim e of the output signal is closely controlled to conform to the targe t range spec if ied in th e ansi tp-pmd standard. 3.1.4 100base-fx receiver admtek inc. 3-7 signal is received th roug h pecl receiver inpu ts from fiber transceiver, an d directly passed to clock recovery circuit for data/c lock recovery. scram b ler/de-scram bler is bypassed in 100base-fx.
ADM7008 function description automatic ? s ignal_dete ct? functio n block due to pin lim itation, ADM7008 doesn?t support sd p/sdn in fiber m o de, which is used to connect to fiber transceiver to indicate there is signal on the fiber. instead, ADM7008 use the data on rxp/rxn to detect consecutiv e 65 ?1? on the receive data (recovered f r om rxp/rxn) to determ ine whether ?s ign a l? is d e tec t ed or not. w h en the detect condition is true (consecutive 65 bits ?1?), internal signal det ect signa l will be asse rte d to inform receive relative b l ocks to be ready for com i ng receive activ ities. 3.1.5 100base-fx transmitter in 100base fx transm it, the serial data str eam is driven out as nrzi pecl signals, which enters fiber transceiver in different ial-pairs for m . fiber transceiver should be available working at 3.3v environment. 3.1.6 10base-t module the 10base-t transceiver module is ieee 802.3 co m p liant. it includes the receiver, transm itter, collision, heartbeat, loopback , jabber, w a veshaper, and link integrity functions, as defined in the standard. fi gure 5 provides an overview for the 10base-t module. the ADM7008 10base-t m odule is com p rise d of the following functional blocks: x manchester encoder and decoder x collision d e tecto r x link test function x transm it driver and receiver x serial and p a rallel interface x jabber and s q e test functions x polarity detection and correction 3.1.7 operation modes the ADM7008 10base-t m odule is capable of operating in either half -duplex m ode or full-duplex mode. in half-duplex mode , the ADM7008 functions as an ieee 802.3 com p liant transceiver with fully integrated filtering. the col signal is asserted during collisions or jabber events, and th e crs signal is asser t ed dur i ng transm it and rece ive. in full duplex mode the ADM7008 can sim u ltaneously transm it and receive data. 3.1.8 manchester encoder/decoder data encoding and transm ission begins when th e transm ission enable inpu t (txen) g o es high and continues as long as the transceiver is in good link state. transm ission ends when the transm ission enable input goes low. the last transition occu rs at the cen ter of the bit cell if the last bit is a 1, or at th e boundary of the bit cell if the last bit is 0. admtek inc. 3-8 a differential inpu t receiver circu it accom p lis hes decoding and a phase -locked loop that separate the manchester-encoded data stream into clock signals and nrz data. the decoder detects the end o f a fram e when no m o re m i dbit tr ans itions are de tected. w ithin one and half bit tim e s aft e r the last bit, carrier sense is deasserted.
ADM7008 function description 3.1.9 transmit d r iver and receiver the ADM7008 integrates all the required signa l conditioning functions in its 10base-t block such that exte rna l f ilters a r e not require d. only one isolation transf orm e r and im pedance m a tching resisto r s are n eeded for the 10base-t transm it a nd receive inte rf ace . the interna l transm it f iltering ensur e s that all the harm onics in the transmission signal are attenuated properly. 3.1.10 smart squelch the sm art squelch circuit is responsible for de term ining whe n valid da ta is present on the differential receiv e . the ADM7008 i m plem ents an intelligent receive squelch on the rxp/rxn differential inputs to ensure that im pulse noise on the receive inputs will not be m i staken for a valid signal. the s quelch circuitry em ploys a com b ination of a m plitude and tim ing m easure m ents (as specified in the ieee 802.3 10base-t standard) to determ ine the validity of data on the twisted-pair inputs. the signal at the start of the pack et is checked by the an alog squelch circu it an d any pulses no t exceeding the squelch level (e ither positive o r negative, depending upon polarity) will be rejected. once this firs t squelch level is overcom e correctly, the opposite sq uelch level must then b e exceeded within 150n s. finally, the sign al must exceed th e original squ e lch level within an additional 15 0ns to ensu re that th e input wavef o rm will no t be re jected. only af ter a ll these con d itions have been sati sfied will a control si gnal be ge nerated to indicate to the rem a inder of the circ uitry that valid data is present. valid da ta is conside r ed to be p r esen t until the squelch level has not been generated f o r a tim e longer than 200 ns, indicating end of pack et. once good data ha s been detected, the squelch lev e ls are redu ced to m i nim i ze the effect of noise, causing prem ature end-of- packet detection. the receive squelch threshold level can b e lowered for use in lo nger cable applications. this is achieved by setting bit 7 of re gister address 10h. 3.1.11 carrier sen s e carrier sens e (crs) is asserted due to receive activity once v a lid data is detected via the sm art squelch function. for 10 mbps half dupl ex operation, crs is a sserted during either packet transm ission or reception. f o r 10 mbps full duplex and repeater mode operations, the crs is asserted only due to receive activity .85 admtek inc. 3-9
ADM7008 function description figure 3-3 1 0 ba se -t blo ck diagr a m and da ta pa th 3.1.12 collision d e tection the smii does not have a collision pin. collis ion is de tecte d inte rn al to the mac, which is generated by an and function of txe n and crs derived from txd and r x d, respec tive l y. the inte rn al mi i will still gene rate the col signal, but th is inf o rm ation is not passed to the amc via the smii. 3.1.13 jabber function 3.1.14 link test f unction the jabber function m o nitors the ADM7008 out put and disables th e tran sm itter if it attem p ts to transm it a longer than legal sized packet. if txen is high for greater than 24m s , the 10base-t transm itter will be disa bled. once disabled by the jabber function, the transm itter stays disabled f o r the entir e tim e that the txen signal is asser t ed. this signal has to be deasserted for approxim a tely 408 m s (the un-jab tim e) before the jabber function re-enables the transm it outputs. th e jabb er fu nction can be disabled by programm i ng bit 0 of regi ster address 10h to high. a link pulse is used to check the integrity of the connection with the remote end. if valid link pulses are not received, the link detect or disables the 10b as e-t twis ted - pair transm itter, receiv e r, an d collision d e tection functions. admtek inc. 3-10 the link pulse generator produces pulses as defined in ieee 802.3 10ba s e-t standard. each link p u lse is nom inally 100ns in duration and is tran sm itted every 16 m s , in the absence of transm it data. setting bit 10 of register 10h to high can disable link pulse check function. m ii t o s m ii c o nvert er rxd sm ii t o mi i c o n v ert e r syn c syn c tx d rec eiv e fi lter cr s rx d [ 3 : 0] rx d v co l rxcl k rxp rx n tx e n tx e r t x d [ 3:0] tx c l k wave sh a p er 10 /1 00 t x dr i v e r tx p tx n pl l cl o c k ph ase ge ne ra t o r 1 0 bas e- t r e c e iv er 10b as e- t t r a n sm it t e r m i i to 1m 8 m a n c h es t er co de en code r n r z t o nrzi 1m8 t o m i i m a nch e s t e r co de dec o d e r smart s q u e lth filt er testm d
ADM7008 function description 3.1.15 automatic link polarity detection ADM7008?s 10base-t transceiver module inco rporates an ?autom a tic link polarity detection circuit?. the inverted polarity is d e term ined when seven consecu tiv e link pulses of inverted polarity or th ree consecutiv e p ackets are re ceived with inverted end-of- packet pu lse s . if the inp u t pola r ity is reve rsed, the erro r con d ition will b e autom a tic ally corrected and reported in bit 13 of register 11h. 3.1.16 clock synthesiz er the ADM7008 im ple m ents a clock synthesizer that generates all th e reference clocks needed from a single external frequency s ource. the clock source m u st be a ttl level signal at 25 mhz +/- 50ppm . 3.1.17 cable broken auto detection the cable broken auto detection feature us e s tim e dom a in reflectom etry (tdr) to determ ine if the cable opens. the t d r test can be performed when the ADM7008 is auto-negotiating or sending 10mbit idle link pulses. after powe r on reset, the ADM7008 transm its link pulses down the pair of an attached cable continuously. the m a gnitude of the r e f l e c tion and th e tim e it takes for the reflection to com e back are recorded. u s ing the recorded inform ation, the cable status and the distance to the broken location can be determ i n ed and are shown in register22.13 and 22.12:11 respectively. if the cab le pr operly term inated th ere will be no re f l ections. if there are no ref l ections it will declare the cable is con n ected prop erly. if m e dium detect function is turn on and the receiv e d sig n al is detec t ed. md in registe r 22:1 0 is ?1?, it will also de clare th e ca ble is not broken. if the cable is connection properl y, the cable length can be determ ined by dsp algorithm s at 100m good link state a nd as indicated in register 22.7:0. admtek inc. 3-11
ADM7008 function description 3.1.18 auto negotiation the auto negotiation function provides a m echanis m for exchanging configuration inform ation between tw o ends of a link segm ent and autom a tica lly sele cting the highest perform a nce m ode of operation supported by bot h devices. fast link pulse (flp) bursts provide the signaling used to communicate au to negotiation abilitie s be tween two de vice s at each end of a link segm ent. for furthe r detail regard in g auto nego tiation, refer to clause 28 of the iee e 802.3u specification. the ADM7008 supports four different ethernet protocols, so the inclusion of auto negotiati on ensures that the highest perform a nce protocol will be selected based on the ability of the link partner. the auto negotiation function within the adm 7008 can be controlled either by internal regis t er access or by the use of configuration pins are sam p led. if disabled, auto negotia tion will not occ u r until sof t ware enable s b it 12 in registe r 0. if auto negotia tion is enabled, the negotiation proce ss will commence immediately. when auto negotiation is enabled, the ADM7008 transm its the abiliti es programm e d i n to the au to n e gotia tion a dvertisem ent reg i ster at address 04h vi a flp bursts. any com b ination of 10 mbits/s, 100 mbits/s, ha lf duplex and full duplex modes m a y be selected. a u to negotiation controls the ex change of configuration inform ation. upon successfully auto negotiation, the abilities repo rted by the link partner are stored in the auto negotiation link partner ab ility register at address 05h. the contents of the ?auto negotiation link partner ability register? are us ed to autom a tically configure to the highest perf orm a nce protocol betw een th e loca l and f a r- end nodes. software can determ ine which m ode has been configured by auto negotiation admtek inc. 3-12 l ow z comparator with positive threshold voltage in trxana, the n the pulse will p ass to phydig. comparator with negative threshold voltage in trxana, the n the pulse will pass to phydig. h igh z
ADM7008 function description by com p aring the contents of register 04h and 05h and then select ing the technology whose bit is set in bo th r e giste r s of highest p r ior i ty relativ e to the f o llowin g list. 1. 100base-tx full duplex (highest priority) 2. 100base-tx half duplex 3. 10base-t full duplex 4. 10base-t half duplex (lowest priority) the basic mode control register at address 0h provides control of en abling, disabling, and restarting of the auto negotia tion function. w h en auto nego tiation is disabled, the speed selection bit (bit 13) controls switching be tween 10 mbps or 100 mbps operation, while the duplex mode bit (bit 8) controls switc hing between full duplex operation and half duplex operation. the speed selection and duplex m ode bits have no effect on the mode of operation when the auto negotia tio n enable bit (bit 12 ) is s e t. the basic mode status register at address 1h indicates th e set of av ailable ab ilities for technology types (bit 15 to bit 11), auto ne gotiation ability (bit 3), and extended register capability ( b it 0 ) . th ese b its are hardwired to ind i ca te the f u ll f unctiona lity of th e ADM7008. the bmsr also provides status on : 1.w hether auto negotia tio n is com p lete (bit 5 ) 2.whether the link partner is advertising th at a remote fault has occurred (bit 4 ) 3.whether a valid link has been established (bit 2) the auto negotiation ad vertisem ent regis t er at address 4h indicates the auto negotia tion abilities to be advertised by the ADM7008. all available abilities are transm itted by default, but writing to this re gister or configuring external pins can suppress any ability. the auto negotiation link partner ability regi ster at address 05h indi cates the ab ilities of the link partner as indicated by auto negotia tion comm unic a tion. the contents of this regis t er a r e considered valid when the auto n e gotia tion c o m p lete bits (bit 5, r e giste r address 1h and bit 4, register 17h) is set. 3.1.19 auto negotiation and speed configuration the twelve sets of four pins listed in table 3-2 configur e the speed capability of each channel of ADM7008. the logic st ate of these pins is latc hed into the advertisem ent register (register address 4h) for auto negotia tion purpose. these pins are also used for evaluating the default value in the base m ode control register (reg is ter 0h) acco rd ing to table 3-2. 3.2 mac interface admtek inc. 3-13 the ADM7008 interfaces to eigh t 1 0 /100 medi a access con t rollers (ma c ) v i a th e r m ii, smii, o r so urce synch r onous mii (ss_smii) inte rface. all ports on th e device operate in the sam e interface m o de that is selected.
ADM7008 function description 3.2.1 reduced media independent interface (rmii) the reduced m e dia independent in terface (rm ii) is com p liant to the r m ii con s ortium ? s rmii rev . 1.2 specification. the refclk pi n that supplies the 50 mhz reference clock to the ad2106 is used as the rmii r e fclk si gnal. all rmii signals with the exception of the assertion of crsdv_ p are synchronous to refclk. figure 3-4 rmii signal diagram 3.2.2 receive path for 100m figure 3-5 shows the relationship among re fclk, crsdv_p , rxd0_p , rxd1_p and rxer_p while receiv i n g a valid packet. carrier sense is d e tected, which causes crsdv_p to assert asyn chronously to refclk . the received data is then placed in to the fifo for resynchronization. after a m i ni m u m of 12 bits are placed into the fifo, the receiv e d data is presented onto rxd[1:0]_p synchronously to refclk. note that w h ile the fifo is filling up r xd[1:0]_p is set to 00 u n til the firs t receiv e d di-bit of preamble (01) is presented onto r xd[1:0]_p . when ca rrier sense is de-asserted at the end of a packet, crsdv_p is de-asserted when the firs t di-bit of a nibble is presented onto rxd[1:0]_p synchronou sly to refclk. if there is still d a ta in the fifo that has not y e t been presented onto rxd[1:0]_p , then on the second di-bit of a nibble, crsdv_p reasse rts. t h is pattern o f assertion a nd de -asse rtion continues until a ll rec e ived data in the fifo has been presented onto r xd[1:0]_p . rxer_p is inactiv e for the duration of the received valid pack et. figure 3-6 shows the relationship among re fclk, crsdv_p and rxd[1:0]_p during a receiv e d false carrier ev ent. crsdv_p is a sserted asynchronously to refclk as in the valid receive case shown in figure 3-5. however , once false carrier is detected, rxd[1:0]_p is changed to (10) (1 1) (v alue 1 1 10 in mii) and rxer_p is asserted. both rxd[1:0]_p and rxer_p transi tion synchronously to refclk . after carrier sens e is admtek inc. 3-14 mac phy tx e n tx d0 tx d1 cr sd v rx d 0 rx d 1 re f c lk rx e r
ADM7008 function description de-asserted, crsdv_p is de-asser ted synchronously to refclk. ref c l k rx d crsd v 00 00 00 00 00 00 01 01 01 01 01 11 dat a dat a dat a da ta da ta da ta dat a dat a dat a 00 rx e r c a rrie r s e ns e det e c t e d 00 00 pr ea m b l e sf d ca r r i e r de ass e r t ed da ta figure 3-5 rmii recep tion withou t error figure 3-6 rmii recep tion w i th false carrie r (10 0 m only ) a receive sy mbol error event is show n in figur e 3-7. the packet with th e sym bol error is trea ted as if it were a v a lid packet with the exc e ption that all d i -bits ar e su bstitu ted with the (01) pattern . figure 3-7 rmii recep tion w i th sy mb ol error admtek inc. 3-15 re f c l k rxd _ p cr s d v _ p 00 00 00 00 10 11 10 11 10 11 10 11 10 11 10 00 00 00 00 00 00 00 rx er_ p c a rrier s e n s e det e c t ed 00 00 f a ls e c a r r ie r c a rrier d e as s e rt ed fa ls e c a r r ier de te ct ed ref c l k rxd _ p crs dv _ p 00 00 00 00 00 00 01 01 data data 00 rx e r _p c a rri e r s e ns e de t e c t e d 00 00 c a rri er d e a sser t e d er ro r d a t a 01 01 01 01 01 01 01 01 01 01 01 rx e rro r de t e c t e d
ADM7008 function description 3.2.3 receive path for 10m figure 3-8 1 0 m rmii rec e iv e diagra m in 10m mode, rxer_p will m a intain low all the tim e due to false carrie r and sy mbol error is not supported by 10m mode. dif f erent from 100m m o de, rxd_p and crsdv_p can transition once per 10 refclk cycl es. after carrier sen s e is de-asserted yet the fif o data is not fully presented onto rxd_p , the crsdv_p de -assertion and re- asser tion a l s o f o llows this rule. 3.2.4 transmit p a th for 100m figure 3-9 shows the relationship among re fclk, txen_p and t xd[1:0]_p during a transm it event. txen_p and txd[1:0]_p are synchronous to refclk. w h en t x en _p is as ser t ed, it indica tes that txd[ 1:0] _p c ontains valid data to be tran sm itted. w h en txen_p is de-asserted, valu e on txd[1:0]_p should be ig nored. if an odd num ber of di-bits are presented onto txd[1:0]_p and txen _p , the final di-bit will be discarded by ad2106. figure 3-9 1 00m rmii tr ansmit diag r a m 3.2.5 transmit p a th for 10m in 10mbse-t m ode, each di-bit m u st be re p eated 10 tim es by the mac, txen_p and txd[1:0]_p should be synchronous to refclk. w h en txen_p is asserted, it indicates that data on txd[1:0]_p is valid for transm ission. in 10base-t m ode, it is possible that the num ber of preamble bits and the num ber of fram e bits received are not in teger nibbles. th e pream ble is always p a dded up such that the sfd appears on the rmii aligned to the nibble boundary . extra bits at the end of the fra m e that do not complete a nibble ar e truncated by ad2106. figure 12 shows the admtek inc. 3-16 ref c l k rx d cr sdv 00 00 dat a t r an si ti on o n c e e v e r y 10 cy cl e s 01 dat a dat a p r ea m b l e / s f d trans i t i on o n c e ev ery 10 c y c l e s ref c l k tx d [ 1 : 0 ] tx e n 00 00 01 01 01 01 01 11 data data data data data data data data da t a 00 00 00 pr e a m b l e sf d data 01 01 01 01
ADM7008 function description tim ing diagram for 10m t r ansm ission. figure 3-10 10m rmii tr ansmit diag r a m recommend v a lue auto ne gotiation capability anend is rec _ 10 m tp_fullduple x e n abl e di sa bl e 10 0 ful l 10 0 hal f 10 ful l 10 h a l f 0 0 1 9 9 9 9 9 0 0 0 9 9 9 0 1 1 9 9 9 0 1 0 9 9 1 0 1 9 9 1 0 0 9 9 1 1 1 9 9 1 1 0 9 9 table 3-2 ch annel con f ig uration 3.2.6 serial and source synchronou s media independent interface the synchronous media indep e ndent in te rface (smii) conform s to the smii specification rev . 2.1. the refclk pin that supplies the 125mhz refe rence clock to the ADM7008 is used as the smii/s erial a nd s ource synchronous media independent interface (s s_smii) reference c l ock . all smii/ss _smii signals are synchronous to r e fclk. the dif f erences between smii and ss_smii are 1. smii shares the sam e sync signal from mac yet ss_smii take tx_sync signal as synchronization input for transm ission a nd output rx_sync to mac for receptio n synchronization usage. 2. smii use r e fclk (125mhz) for both rece ive and transmit blocks. s s _smii takes txclk as transm it block reference clock and output an 125mhz rxclk to mac for receiv e usag e. all signals output fr o m ADM7008 are synch r onous to rxclk. in th is m o de, refclk will b e div i ded by 5 to generate 25 m clock bef o re it is f e d into ADM7008 internal pll block. ss_smii m ode is enabled b y setting rsmode1 (pin 43) admtek inc. 3-17 ref c l k t xd_ p tx e n _ p 00 00 d a t a tr a n s i t i on on c e ev e r y 10 c y cles 01 da t a da t a p r ea m b l e /s f d t r a n s i t i o n on ce eve r y 10 cy cl es
ADM7008 function description to low and placing a pull up resistor on crsdv_p6. in this m o d e , crsdv_ p [3] becom e s rx_sync, crsdv_p4 becom e s rxclk and txen_p4 acts as tx_sync. figure 3-11 smii signal diagram figure 3-12 ss_smii sig n al diagram 3.2.7 100m receive path received data and control inform ation is groupe d in 10-bit segm ents that are delim ited by the sync signal in smii m ode (or sync_ r x in ss_smii mode) as shown in figure 15. each segm e n t represents a new byte of data. figure 3-13 100m smii receiv e timing diagram in ss_smii m ode, refclk and sync ar e no longer common for bot h transm it and receiv e blocks. they are renam e d to rxclk and rx_sync. figure 3-14 100m ss_s m ii receiv e timing diagram admtek inc. 3-18 re f c l k r xd_ p sync r xd7 cr s r xdv rx d 0 r xd1 rx d 2 r xd3 rx d 4 rx d 6 r xd7 r xd5 cr s r xdv r xd0 r xd1 r xd2 r xd3 r xd4 r xd6 r xd7 r xd5 cr s r xdv r xd0 r xd1 r xd2 ma c phy sy n c tx d 0 _ p [7 :0 ] r x d0_p[ 7 : 0 ] re f c l k ma c ph y t x c l k_ ss m i i sy n c _t x t x d 0 _ p [7 :0 ] rx cl k _ s s m i i sy n c _r x rx d0 _ p [ 7 : 0 ] rxclk _ s s m i i rxd _ p sy nc _ r x rx d 7 cr s rx d v rx d 0 rx d 1 rx d 2 rxd3 rxd4 rxd6 rxd7 rxd5 cr s rx d v rxd0 rxd1 rxd2 rxd3 rxd4 rxd 6 rxd 7 rxd 5 cr s rx d v rxd 0 rxd 1 rxd 2
ADM7008 function description in smii m o de, when rxdv bit is high, rxd[7: 0] are used to convey packet data; when rxdv bit is low , rxd[7:0] are carrying ph y status. see t a ble 3-3 for more detail. c r s rx d v rx d 0 r x d 1 rx d 2 r x d 3 r x d 4 r x d 5 r x d 6 rx d 7 x 0 r x e r f r o m previous f r am e s p eed 0 = 10mb/s 1 = 100mb/s duplex 0 = h a lf 1 = full link 0 = down 1 = up jabber 0 = o . k. 1 = error upper nibble 0 = inv a lid 1 = v a lid fa lse carrier 0 = no 1 = detected 1 x 1 one data by te (t w o m i i dat a nib b le) table 3-3 re ceiv e data encoding for smii/ss_smii mode 3.2.8 10m receiv e path sim ilar to 100m receiv e path excep t that each segm ent is repeated 10 tim e s. the mac can sam p le any one of every 10 segm ents in 10base-t mode. the mac also has to generate a s ync pulse once every 10 clock cycles. figure 3-15 10m smii re ceiv e timing diagram figure 3-16 10m ss_smii receiv e timing diagra m admtek inc. 3-19 re f c l k r xd_ p s ync rx d7 _ 0 crs_ 1 rx dv_ 1 rx d0 _ 1 rx d1 _ 1 rx d2 _ 1 rx d3 _ 1 rx d4 _ 1 rx d6_ 1 rx d7 _ 1 rx d5_ 1 cr s _ 1 rx dv_ 1 rx d0 _ 1 rx d1 _ 1 rx d2 _ 1 rx d3_ 1 rx d4_ 1 rx d5_ 1 rx d6 _ 1 rx d7 _ 1 cr s _ 2 rx dv_ 2 rx d0 _ 2 data repeat ed 10 t i m e s ( u se 10 s y n c f o r 1 b y te data) r x cl k _ ssm i i rx d _ p sync _ r x rx d7_ 0 cr s _ 1 rx dv_ 1 rx d0 _ 1 rx d1 _ 1 rx d2 _ 1 rx d3 _ 1 rx d4 _ 1 rx d6 _ 1 rx d7_ 1 rx d5 _ 1 crs _ 1 rx dv _ 1 rx d0 _ 1 rx d1 _ 1 rx d2 _ 1 rx d3 _ 1 rx d4 _ 1 rx d5_ 1 rx d6_ 1 rx d7_ 1 crs _ 2 rx dv_ 2 rx d0 _ 2 d a ta re pea te d 10 t i m e s ( u se 10 sy nc_rx fo r 1 b y te d a ta)
ADM7008 function description 3.2.9 100m transmit path sim ilar to 100m receive path, transm it data is grouped in 10-bit segm ents that are delim ited b y the sync signal (or tx_s ync in ss_smii m ode), each seg m ent represents a new byte of data. see figur e 3-17 for 100m smii transm it tim ing diagram and figure 3-18 for ss_smii tim i ng diagram . in ss_smii m ode, refclk and sync are no longer commonly used for both transm it and receive blocks. they are renam e d to txcl k and tx_ s ync. w h en txen bit is low , data o n txd[7:0] will be ig nored by ADM7008. see t a ble 3 - 4 tran sm it data encoding for m o re detail. figure 3-17 100m smii transmit timing diagram figure 3-18 100m ss_s m ii transmit timing diagram 3.2.10 10m transmit path in 10base- t m ode, each segm ent must be rep eated 10 tim es by the mac. in this mode, the mac must generate the sam e data in each of the 10 segm ents. ADM7008 will sam p le the incom i ng data at the 5 th s ync (or sync_tx) location. figure 3-19 10m smii transmit timing diagram admtek inc. 3-20 re f c l k t xd_ p s ync txd 7 t xer t xen tx d 0 tx d 1 tx d 2 tx d 3 tx d 4 txd 6 txd 7 tx d 5 t xer t xen tx d0 tx d 1 tx d 2 tx d 3 tx d 4 tx d 6 txd 7 tx d 5 t xer t xen tx d0 tx d 1 tx d 2 t x c l k _ ssm i i txd_ p s ync _ t x txd 7 t xer t xen tx d 0 tx d 1 tx d 2 tx d 3 tx d 4 txd 6 txd 7 tx d 5 t xer t xen tx d0 tx d 1 tx d 2 tx d 3 tx d 4 tx d 6 txd 7 tx d 5 t xer t xen tx d0 tx d 1 tx d 2 re f c l k t xd_ p s ync tx d 7 _ 0 tx e r _ 1 tx e n _ 1 tx d 0 _ 1 tx d 1 _ 1 tx d 2 _ 1 tx d 3 _ 1 tx d 4 _ 1 tx d 6 _ 1 tx d 7 _ 1 tx d 5 _ 1 tx e r _ 1 tx e n _ 1 tx d 0 _ 1 tx d 1 _ 1 tx d 2 _ 1 tx d 3 _ 1 tx d 4 _ 1 tx d 5 _ 1 tx d 6 _ 1 tx d 7 _ 1 tx e r _ 2 tx e n _ 2 tx d 0 _ 2 data repeat ed 10 t i m e s ( u se 10 s y n c f o r 1 b y te data)
ADM7008 function description figure 3-20 10m ss_smii transmit timing diagra m 3.3 led display register 19 is used for differe nt m o de led display. there are two kind of led display m echanis m s provided by ADM7008: single and du al color led m ode, either m ode provide power on led self test to m i ni m i ze and ease th e system test cost. 3.3.1 single color led when single color led is programmed (dualled is set to low during power on reset), all po rts le d will be of f during power on rese t (output va lue sam e as recommend value on led pins). after power on reset, all inte rnal parallel leds will be on for 2 seconds, intern al parallel led status will be stream ed out through led_data a nd this sign al is output by ADM7008 at the falling edge of led_c lk. be fore describing the serial led output data form at, we tend to describe the m eaning of internal parallel leds. there are three types of led supported by ADM7008 internally. the first is lnkact , which represents the status of link a nd tran sm it /receive activity; the second is ldspd, which indicates the speed status and the last is dupcol, which shows pure duplex status in full duplex and duplex/collisi on com b ined status in half duplex. all these three led can be controlled by register 19 to change display contents. after led self tes t , table 3-4, 3-5 and 3-6 s how the on/off polarity acco rdin g to different recomm ended value setting for ldspd, dupcol and lnkact. w h e n the recomm end value is high, ADM7008 will driv e led low ; ADM7008 will driv e the led high when the recomm end value is low, instead. s p e e d l d s p d 10m 0 10 0m 1 link fail 1 table 3-4 speed led dis p la y du ple x d u pc o l admtek inc. 3-21 t x c l k _ ssmi i t xd_ p s ync _ t x t x d7 _ 0 tx e r _ 1 tx e n _ 1 t x d0 _ 1 t x d1 _ 1 t x d2 _ 1 t x d3 _ 1 t x d4 _ 1 t x d6 _ 1 t x d7 _ 1 t x d5 _ 1 tx e r _ 1 tx e n _ 1 t x d0 _ 1 t x d1 _ 1 t x d2 _ 1 t x d3 _ 1 t x d4 _ 1 t x d5 _ 1 t x d6 _ 1 t x d7 _ 1 tx e r _ 2 tx e n _ 2 t x d0 _ 2 da t a r e pe at e d 10 t i m e s ( u se 1 0 s y n c _rx f o r 1 b y t e da t a )
ADM7008 function description h a l f f u l l link up blin k (high) wh en c o llisio n low all th e ti m e link fail high all th e ti m e high all th e ti m e table 3-5 du plex led dis p la y link/activi ty speed l i n k a c t i v i t y lin k up lo w blink ( h ig h) whe n r x /tx link fail high all th e ti m e high all th e ti m e table 3-6 ac tiv i t y /link l e d displa y blinking time is programm ed through bli nk_tm[1:0] in register 19 bit 13 to 12. com b ined with detec t e d speed with in each port, dif f erent blinking tim e will be determ ined and this dif f erent blinking tim e can be used to distinguish the speed. blinking time is summ arized in t a ble 3-7. blinking time blink_ t m 10 m 1 0 0 m 00 10 0 m s 10 0 m s 01 20 0 m s 10 0 m s 10 40 0 m s 10 0 m s 11 10 0 m s 50 m s table 3-7 differe n t blinki ng time for differen t sp eed besides duplex, speed, link and activity status, a d m7008 also provides cable inform ation that can be shown on leds when register 19 is programm e d t o distance led display (see t a ble 3-8). lnk a c t d u pc o l ledsp d ca b l e dis t a n c e 1 1 0 0 t o 4 0 m e t e rs 1 0 0 40 t o 8 0 m e t e rs 0 0 0 80 t o 1 2 0 m e t e rs 1 1 1 c a bl e b r oke n table 3-8 ca ble dista n ce led displa y admtek inc. 3-22
ADM7008 function description 3.3.2 dual color led when dual color led is programmed (duall e d is set to high dur ing power on reset), all ports led will be off during power on reset (output high on lnkact and ldspd and output recommend value on dupcol). afte r power on reset, al l leds will be on for 1 secon d s to test 1 0 m m ode lnkact /ldspd connection and on for another 1 second to test 100m mode lnkact/ldspd wire connec tion. t h is period allow m a nufacture operator to check whether the led wire connection on pcb board is correct or not. after led self-tes t, table 3-9 and table 3 - 10 show the on/off polarity according to different speed detected by ADM7008. dupcol is alw a ys set to single color mode display no m a tter the value of dualled is. s p e e d l d s p d 10m 0 10 0m 1 link fail 1 table 3-9 speed led dis p la y link/activi ty speed l i n k a c t i v i t y 10 0m l i nk u p lo w b l i nk ( h ig h) whe n r x / t x 1 0 m link _up h i gh blin k (low ) w h en rx /tx link fail high all th e ti m e high all th e ti m e table 3-10 activ i t y /link l e d displa y cable length led display m ode controlled by regis t er 19 will be dis a bled when dual color m ode is selected, by not displayi ng cable length, instea d, ADM7008 display led status by default setting, i.e., l nka ct for link/activity led, dupcol for duplex/collision display and ldspd for speed indication. refer to table 3-7 for dual color blinking tim e. 3.3.3 serial ou tput led status admtek inc. 3-23 intern al led status will be stream ed output through two pi ns ? led_data and led_cl k , where led_dat a is used to i ndicate internal 8 port led status and synchronous to led_clk. serial led output sequence is programmed through dual led during power on reset. rsmode1 also affects the sequence of led_ d ata and will be describ e d as f o llows.
ADM7008 function description 3.3.4 rmii mode (rsmode1 = 1) figure 3-21 stream led under rmii mode 3.3.5 smii/ss_smii mode (rsmode1 = 0) figure 3-22 stream led under smii/ss_smii mode the high duration for led_clk is 40ns and the low duration is 600ns to for m 640ns period clock . ADM7008 will burst 24 bit s t atus in one tim e in order to display internal link/activity, duplex /collision an d speed status acco rdin g to differen t m ode. w h en a burst is co mpleted, l e d_clk will keep lo w for 40 m s and system can use it to distinguish between two bursts. 3.4 management register access the smi consists of two pins, managem e nt data clock (mdc) and m a nage m e nt data input/output (mdio). the ADM7008 is de signed to support an mdc frequency specified in the ieee specification of up to 2.5 mhz. the mdio lin e is bi-directional and m a y be shared by up to 32 devices. the mdio pin requires a 1.5 k ? pull-up which, during idle and turnaround periods, will pull mdio to a logic one state. each mii m a nagem e nt data fram e is 64 bits long. the first 32 bits are pream ble consisting of 32 contiguous logic one bits on mdio and 32 corresponding cycles on mdc. following preamb le is the start-of-frame field indicated by a <01> pattern. the next fi eld signals the operation code (op) : <10 > ind i cates read from mii managem e nt register operation, and <01> indicates write to mii m a nagem e nt register operation. the next two fi elds are phy device address and mii m a nagem e nt regis t er add r ess. both of them are 5 bits wide and the m o st signifi can t bit is transf er red fi rst . admtek inc. 3-24 le d _ c l k le d _ d a t a dup c o l 0 du p c o l 1 du p c o l 2 du p c o l 3 du p c o l 4 du p c o l 5 du p c o l 6 du p c o l 7 du p c o l 0 spe e d0 spe e d1 spe e d2 spe e d3 spe e d4 spe e d5 spe e d6 spe e d7 ln kac t 0 ln kac t 1 ln kac t 2 ln kac t 3 l n kac t 4 l n kac t 5 l n kac t 6 l n kac t 7 le d _ c l k le d _ d a t a dup c o l 0 du p c o l 1 du p c o l 2 du p c o l 3 du p c o l 4 du p c o l 5 du p c o l 6 du p c o l 7 du p c o l 0 ln kac t 0 ln kac t 1 ln kac t 2 ln kac t 3 ln kac t 4 ln kac t 5 ln kac t 6 ln kac t 7 spe e d0 spe e d1 spe e d2 spe e d3 spee d4 spee d5 spee d6 spee d7
ADM7008 function description during read operation, a 2-bit turn around (ta) tim e spacing between the register address field and data field is provided for the mdio to avoid contention . following the turnaround tim e , a 16-bit data stream is read from or written into the mii m a nagem e nt registers of the ADM7008. 3.4.1 preamble s uppression the ADM7008 supports a pream ble suppression m ode as indicated by an 1 in bit 6 of the basic m ode status reg i s t er (reg ister 1h). if the station m a nagem e nt entity (i.e. ma c or other m a nagem e nt controller) determ ines that all phys in the system support preamble suppress i on by reading a 1 in this bit, then the station m a nage m e nt entity need s not generate pream b le for e ach m a nagem e nt transaction. the ADM7008 r e quires a single initialization sequence of 32 bits of pream bl e following powerup/hardware reset. this requirem e nt is generally m e t by pulling-up th e resistor of mdio. w h ile the ADM7008 will respon d to m a nagem e nt accesses withou t pream ble, a m i ni m u m of one idle bit between m a nagem e nt transactions is required as specified in ieee 802.3u. when ADM7008 detects that th ere is phys ical address m a tch, then it will enable read/w rite capability for external access. w h en neither p hysical add r ess nor register address is matched, th en ADM7008 will tri-state the mdio pin. figure 3-23 smi read o p era t ion 3.4.2 reset operation the ADM7008 can be reset either by hardware or software. a hardware reset is accom p lished by applying a negative pulse, with dur ation of at least 200 m s to the rc pin of the ADM7008 during norm a l operation to guar antee internal power on reset circuit is res e t well. sof t ware r e set is ac tiv ated by se tting the re set bit in the ba sic m ode control register (bit 15, register 0h). th is bit is self-clearing and, when set, will return a value of 1 until the s o f t ware rese t opera tion has com p le ted, please n o te tha t inte rnal sram will not be reset during software reset. figure 3-24 smi write o p era t ion admtek inc. 3-25 md c mdi o ( m a c ) m d i o (p hy) z 0 1 1 0 0 1 1 0 0 0 0 0 0 0 z 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 z pream bl e s t a r t op c o d e ( r e ad) phy add r es s ( 5 ' h0c i n t h i s ex am pl e ) r egi s t er a d dr es s ( 5 'h0 0 i n t h i s ex am pl e ) t a regi st er d a t a (16' h 1300 in t h i s ex am pl e) md c mdi o ( m a c ) z 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 z pream bl e s t a r t op c o d e (w ri t e ) phy add r es s ( 5 ' h0c i n t h i s ex am pl e ) r egi s t er a d dr es s ( 5 'h0 0 i n t h i s ex am pl e ) t a regi st er d a t a (16' h 1300 in t h i s ex am pl e) 0
ADM7008 function description hardware reset operation sam p les the pins and initializes all reg i ste r s to their def a ult values. this process includes re-evaluation of all hardware configur abl e re gi st e r s. a hardware reset affects all the eight p hys in the device. a software reset can res e t an individual phy and it does not la tch the externa l p i n s nor reset the r e g i ste r s to their respe c tiv e def a ult valu e. logic levels on several i/o pi ns are detected during a hard ware r e set to dete rm ine the initial functionality of ADM7008. som e of these pins are us ed as output ports after reset operation. care m u st be taken to ensure that the conf iguration setup will not inte rf ere with no r m al operation. dedicated configur ation pins can be tied to vcc or ground directly. configuration pins m u ltiplexed with logic level output functi ons should be either weakly pulled up o r weakly pulled down through resisto r s. configuration pins multiplexed with led outputs should be set up with one of th e following circuits shown in figure 3-24. 3.5 pow e r management there are two types of power sa ving m ode provided by ADM7008: receive power saving (so called medium detect power saving) and transm it power saving mode (so called low power link pulse power saving m o de). 3.5.1 medium detect pow er saving an analog block is designed for carrier sense detecting. when there is no carrier sense presented on m e dium ( cable not attached), then ?signal detect? will not be on. whenever cable is attached to ADM7008 and the voltage threshold is above +/- 50m v , then sd will be asserted high to indicate th at there is cab le attached to ADM7008. all intern al blo c ks except m a nagem e nt block will b e disabled (re s e t) bef o re s d is asser t ed . w h e n s d i s a s s e r t e d , i n t e r n a l a u t o n e g o tiation block will be turned on and the 10m transm it driver will also be turn ed o n for au to n e gotia tion p r ocess. auto negotia tion will issue contro l signals to control 10m receive and 100m a/d block according to diffe rent state in arbitration block diagram . duri ng auto negotiation, all digital blocks except m a nage m e nt and link m o nitor b l ocks will be disab l ed to reduce power con s um ption. whenever operating speed is determ ined (eith er auto negotiation is on or off), the non- active spee d rela tive c i rcuit will be disabl ed all th e tim e to save more power. for exam ple, when corresponding port is operati ng on 10m, then 100m re lative blocks will be disab l ed and 10m re lative b l ocks will be d i sa bled whene v er cor r espo nding port is in 100m m ode . auto negotiation block will be rese t when sd signal goes from high to l o w. see figure 3 - 25 for the s t ate d i agram for this algo rithm . admtek inc. 3-26
ADM7008 function description 3.5.2 transmit p o w er saving in ADM7008, enabling tx power saving feature could save transm it power before any link partner trying to link up. two transm it powe r saving m e thods are applied to ADM7008 by regis t er 17 .5 configuration. w h en setting register 17.5 to ?0 ?, the trans m it- driver will lower the driving cu rrent all th e tim e to save power before the receiv e r detects signals com i ng in. w h en setting to ?1 ?, ADM7008 transm it low-power link pulse (llp) to the cable. the wavefor m of llp is the sam e as nlp and flp, the difference is the period of llp is around 100m s . beside s the longer period, adm 7008 also lower the transm it-dr iving curr ent between sen d ing a pulse and a pulse. the tx power saving feature is activated by setti ng ADM7008 of n-wa y or 10m ca pabilities. see figure 3-26 for referenc e. figure 3-25 medium de tect po w e r m a nagem e nt flo w char t another way to reduce instant power is to separate the led display period. all 24 leds will be divid e d into 24 tim e fram e and each tim e fram e occupies 1 us. one and only one led will be driven a t ea ch tim e f r ame to re duc e instant cu rre nt consum ed f r om led. admtek inc. 3-27 idle disall = 1 encardet = 1 carrier ? yes sd = 1 enanen = 1 pwr_rst || software_rst auto negotiation process yes no
ADM7008 function description figure 3-26 lo w po w e r link pulse during tx for po w e r man a gement 3.6 voltage regulator ADM7008 requires two different levels, 3.3v and 1.8v, of voltage supply to provide the power to different parts of circuitry in side the chip. ADM7008 ha s a build-in voltage regulator circuitry to generate the 1.8v volta ge from 3.3v power source. therefore, an external pnp power transisto r is als o needed and the block diagram of voltage regulator is shown as below. admtek inc. 3-28 flp = 80 m a (an) nlp = 80 m a (10m ) m l t3 = 40 m a (10 0 m ) drv on = 1 pw _ save_ tx = o ff o r m edi um det ec t = on or for c e _ good_li nk=on i n 10 m o r forc e i n 100m m ode pw _ save_ tx = o n a n d m e di um det ec t = off and (a ut o negi at i on enabl e = on or fo rc e i n 10m m ode ) and force_good_li nk =o ff if 10 m m ode nlp = 60 m a (10 m ) flp = 60 m a (a n ) drv on = 0 rg16drv 62m a = off llp = 20 m a or 60 m a (a n or 10m ) drv on = 0 rg16d rv 62m a = on id l e tx pw savin g mo d e
ADM7008 function description figure 3-27 extern al pnp po w e r tr a n sistor diag ram admtek inc. 3-29 r1 r2 b a nd- gap r e f e r e nce v o l t a ge gener a t o r v ref co n t r o l v 3. 3 v v re f v 1. 8v r2 r1 + r 2 i n t e r n al c i r cui t of r egul at or pn p p o w e r tr an si st or v 1. 8v
ADM7008 register description chapter 4 register description note: please refer to section ? 1.5.2 register type descriptions ? for an explanation of pin abbrevia tion s . 4.1 register mapping admtek inc. 4-1 a d d r e s s r e g i s t e r n a m e d e f a u l t 0 h c o n t r o l r e g i s t e r 3 0 0 0 1 h s t a t u s r e g i s t e r 7 8 4 9 2h ? 3h phy identifier register cc42002e 4h auto negotiation advertisem ent register 01e1 5h auto negotiation link p a rtner ability register 01e1 6h auto negotiation expansion register 0000 7h - fh reserved reserved 10h phy control register 1000 11h phy 10m configuration register 0008 12h phy 100m configuration register 0022 13h led configuration register 0a34 14h interrupt enable register 03ff 16h phy generic status register 0000 17h phy specifi c status register 0060 18h recomm end value storage register 0000 19h global interrupt st atus register 0000 1dh receive error counter 0000 1eh chip id register ?at? 8818 1fh global interrupt register (o nly available in port 0) 0000
ADM7008 register description 4.2 register bit mapping 4.2.1 register #0h -- control register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 r s t l p b k spd_ l a n e n p d n i s o rstar d p l x coltst spdmsb 0 0 0 0 0 0 r/w r/w r / w r / w r / w r/ w r/w p i n r / w r/w r o r o r o r o r o r o 4.2.2 register #1h ? status register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 capt4 t x f u l t x h a l f t f u l t h a l f c a p t 2 0 0 0 mfsup ancomp rmflt a n e n l i n k j a b extcap r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.3 register #2h ? phy id register (002e) 4.2.4 register #3h ? phy id register (cc11) 4.2.5 register #4h ? advertisement register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 n p a g e 0 r f 0 as m_d i r pa u s e t 4 fd x 1 0 0 h d x 100 fd x 1 0 h d x 1 0 0 0 0 0 1 r/w r o r / w r o r / w r/w r o r/w r/w r / w r / w r o r o r o r o r o 4.2.6 register #5h ? link partner ability register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 n p a g e a c k r f 0 l p _d i r l p _pa u l p _t 4 l p _fd x l p _h d x l p _f1 0 l p _h 1 0 0 0 0 0 1 r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.7 register #6h ? auto ne gotiation expansion register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 p d f l t l p n p a b n p a b l e p g r c v lpanab r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.8 register #7h ? # fh re served 4.2.9 register #10h ? phy configuration register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 i f s e l 0 0 0 0 0 0 0 0 0 0 xoven 0 0 0 dispmg r o r o r o r o r o r o r o r o r o r o r o r/w r/w r/w r o r/w admtek inc. 4-2
ADM7008 register description 4.2.10 register #11h ? 10m configuration register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 drv62ma a p d i s e n r j a b distj a b n t h fgdlnk r o r o r o r o r o r o r o r o r o r o r/w r/w r / w r/w r / w r/w 4.2.11 register #12h ? 100m configuration register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 se l f x 0 0 disscr e nfefi 0 1 0 r o r o r o r o r o r o r o r o r/w r o r o r / w r/w r o r o r o 4.2.12 register #13h ? led configuration register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 lnkc3 lnkc2 lnkc1 l nkc0 dupc3 dupc2 dupc1 dupc0 spdc3 spdc2 spdc1 spdc0 r o r o r o r o r/w r/w r/w r/w r/w r / w r / w r / w r/w r/w r/w r / w 4.2.13 register #14h ? interrupt enable register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 xovc hg s p d c h g dup c h g p gr c h g l nkc h g s y mer r fcar four u n t j ab i n t r j ab i n t r o r o r o r o r o r o r/w r/w r/w r / w r / w r / w r/w r/w r/w r / w 4.2.14 register #16h ? phy generic s t atus register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 c b b r k brk1 brk0 m d f x e n xover cblen7 cblen 6 cblen5 cblen4 cblen3 cblen2 cblen1 cblen0 r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.15 register #17h ? phy specific status register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 j a b r x j a b t x polar p auout p a u i n duplex s p e e d l i n k r e c p a u r e c d u p r e c s p d recan r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.16 register #18h ? recommend value storage register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 pw r d n r e c a n s e l f x rec1 00 re c f u l p a u r e c disfefi xoven xover r m ii_s m ii repeat er phya4 phya3 p h y a 2 p h y a 1 p h y a 0 r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.17 register #19h ? int errupt status register 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 xovc hg s p d c h g dup c h g p gr c h g l nkc h g s y mer r fcar four u n t j ab i n t r j ab i n t r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o admtek inc. 4-3
ADM7008 register description 4.2.18 register #1 dh ? receive error counter 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 e r b 1 5 e r b 1 4 e r b 1 3 e r b 1 2 e r b 1 1 e r b 1 0 e r b 9 e r b 8 e r b 7 e r b 6 e r b 5 e r b 4 e r b 3 e r b 2 e r b 1 e r b 0 r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.19 register #1eh ? chip id (8888 ) 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 cid 3 3 cid 3 2 c i d 3 1 c i d 3 0 c i d 2 3 cid 2 2 cid 2 1 cid 2 0 cid 1 3 c i d 1 2 c i d 1 1 c i d 1 0 cid 0 3 cid 0 2 cid 0 1 c i d 0 0 r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.2.20 register #1 fh ?total in terrupt sta t us (only for port 0) 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 i n t 7 i n t 6 i n t 5 i n t 4 in t 3 in t 2 in t 1 in t 0 0 0 0 0 0 0 0 0 r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o r o 4.3 register description 4.3.1 control (register 0h ) admtek inc. 4-4 bit # name description type default interface 1 5 r s t r ese t 1: phy res e t 0: norm al operation setting this bit in itiates the sof t ware reset function that resets the selected port, except for the phase-locked loop circuit. it will re -la t ch in all hardware configuration pin values. the software reset process takes 25us to com p lete. this bit, which is self-clearing, returns a value of 1 until the re set process is com p lete. r/ w sc 0 h 1 . u p d a t e d b y mdc/mdio. 2.connect to central control block to generate reset signal. 1 4 l p b k b ack enable 1:enable loop back m ode 0: disable l oop back mode this bit controls the phy loop back operation that isolates the network transm itter o u tputs (txp and txn) and routes the m ii transm it data to the m ii receiv e data path. this function sho u ld onl y be used when auto ne g otia tion is r/ w 0 h 1 . u p d a t e d b y mdc/mdio only. control the w i re connection in driver
ADM7008 register description bit # name description type default interface admtek inc. 4-5 disabled (bit12 = 0). the specific p hy (10base-t or 100base-x ) used for this operation is determ ined by bits 12 and 13. 1 3 s p e e d _ l s b speed selection lsb 0.60.13 0 0 10 mbps 0 1 100 mbps 1 0 1000 mbps 1 1 reserved link speed is selected by this bit or by auto negotiation if bit 12 of this register is set (in wh ich case, the value of this bit is ignored). r/ w 1 h w h e n a u t o n egotiation is enable, th is pin has no effect. 1 2 a n e n a uto negotiation enable 1: enable auto negotiation process 0: disable a u to negotiation process this bit de te rm ines whether the link speed should set up by the auto negotiation process or not. it is set at p ower up or reset if the p i _recanen p in detec t s a logic 1 inpu t leve l in twisted-pair mode. r/ w 1h this bit anded with pi_recanen p in dete rm ines auto negotiation capability of phy841f. 1 1 p d n p ower down enable 1: power down 0: norm al operation ored result with pi_pwrdn pin. setting this bit high or asserting the pi_pw r dn puts the ph y841f into p ower down m ode. during the power down m ode, txp/txn and all led outputs are tri-s t ated and the mii/rm ii interfaces are isolated. r/ w 0 h 1 . o n l y access through mdc/mdio 1 0 i s o i solate phy841f from network 1: isolate p hy from mii/rmii 0: norm al operation setting this control b it is olates the pa rt from the rmii/mii, with the exception of the serial m a nagem e nt interface. w h en this bit is asserted, the p hy841f does not respond to t xd, txen and txer inputs, and it presents a high im pedence on its txc, rxc, crs dv, rxer, rxd, col and crs outputs. r/ w 0 h 1 . o n l y access through mdc/mdio 2.used to reset corresponding port.
ADM7008 register description bit # name description type default interface 9 a n e n _ rs t r estart auto negotiation 1: restart auto negotiation process 0: norm al operation setting this bit while auto negotia tio n is enabled forces a new auto negotiation p rocess to start. this b i t is self -c lea r ing and returns to 0 afte r the auto negotiation p rocess has commenced. r/ w sc 0 h 8 d p l x d uplex mode 1: full duplex m ode 0: half duplex m ode if auto negotiation is disabled, this bit determ ines the duplex mode for the link. r/ w 0h this bit ored with recf ul p in dete rm ines the duplex capability of phy841f when anen disa bled. 7 c o l t s t collision te st 1: enable c o l signal test 0: disable c o l signal test w h en set, th is bit will c a u se the col signal of mii interface to be asserted in response to the assertion of txen. r/ w 0 h 6 s p e e d _ m sb speed selection msb set to 0 all the tim e indicate th at th e phy841f does not support 1000 mbps function. r o 0 h a l w a y s 0 . 5 : 0 r e s e r v e d r o 0 0 h always 0 . 4.3.2 status (register 1h ) admtek inc. 4-6 bit # name description type default interface 1 5 c a p _ t 4 100base-t4 capable set to 0 all the tim e to indicate that the phy841f does not support 100base-t4 r o 0 h 1 4 c a p _ t x f 100base-x full duplex capable set to 1 all the tim e to indicate that the phy841f does support full duplex mode r o 1 h 1 3 c a p _ t x h 100base-x half duplex capable set to 1 all the tim e to indicate that the phy841f does support half duplex mode r o 1 h 1 2 c a p _ t f 10m full d uplex capable tp : set to 1 all th e tim e to indic a te that the phy841f does support 10m full r o 1 h
ADM7008 register description bit # name description type default interface admtek inc. 4-7 duplex m o de fx : set to 0 all th e tim e to indic a te that the phy841f does not support 10m full duplex m o de 1 1 c a p _ t h 10m half duplex capable tp : set to 1 all th e tim e to indic a te that the phy841f does support 10m half duplex m o de fx : set to 0 all th e tim e to indic a te that the phy841f does not support 10m half duplex m o de r o 1 h 1 0 c a p _ t 2 100base-t2 capable set to 0 all the tim e to indicate that the phy841f does not support 100base-t2 r o 0 h 9 : 7 r e s e r v e d r o 0 h 6 c a p _ s u p r mf preamble suppression capable this bit is h a rdwired to 1 indica ting that the phy841f accepts m a nagem e nt fram e without preamble. minimum 32 p ream ble bits are required following p owe r -on or hardware reset. one idle bit is required between any two m a nagem e nt transactions as per ieee 802.3u specification . ro 1h use to control mdc/mdio state ma chine. 5 a n _ c o mp a uto negotiation complete 1: auto negotiation process com p leted 0: auto negotiation process not com p leted if auto negotiation is enabled, this bit indicates whether th e auto negotiation p rocess has been com p leted or not. set to 0 all the tim e when fiber mod e is selected. r o 0 h status u p d a t e d by auto n egotiation control block. 4 r e m _ f l t r emote fault detec t 1: rem o te fault detected 0: rem o te fault not detected this bit is la tched to 1 if the rf bit in the auto negotiation link partner ability register (bit 13, regist er address 05h) is set or the receive chann e l m eets the far end fault indication func tion criteria. it is unlatched w h en this register is read. r o 0 h status u p d a t e d by auto n egotiation control block 3 c a p _ a n e g a uto negotiation abilit y 1: capable of auto negotiation r o 1 h
ADM7008 register description bit # name description type default interface 0: not capable of auto negotiation tp : this bit is set to 1 all the tim e , indicating that phy 841f is capable of auto negotiation. fx : this bit is se t to 0 a ll the tim e, indicating that phy 841f is not capable of auto negotiation in fiber mode. 2 l i n k l ink status 1: link is up 0: link is down this bit reflects th e current state of the link -test-fail state m achine. loss of a valid link causes a 0 latc hed into th is bit. it rem a ins 0 until this reg i ste r is read by the serial m a nagem e nt interface. whenever linkup, this bit should be read twice to get link up status ro, ll 0h updated by per p ort link monitor 1 j a b j abber detect 1: jabber condition detected 0: jabber condition not detected ro, lh 0h updated by per p ort jabber detector 0 e x t r e g e xtended capability 1: extended register set 0: no extended register set this bit def a ults to 1, ind i cating tha t the phy841f i m ple m ents extended registers. r o 1 h 4.3.3 phy identifier register (register 2h) bit # name description type default interface 1 5 : 0 p h y - id[15:0] ieee address ro 002e rg2_phy_i d input 4.3.4 phy identifier register (register 3h) admtek inc. 4-8 bit # name description type default interface 1 5 : 1 0 p h y - id[15:0] ieee address/model no./rev. no. ro cc10 rg3_phy_ i d input 9 : 4 m o d e l [ 5 : 0] admtek phy revision id. ro cc10 rg3_model_i d input 3 : 0 r e v - id[3: 0 ] admtek phy revision id. r o 4 h 0 rev_id i n p u t
ADM7008 register description 4.3.5 advertisement (register 4h) admtek inc. 4-9 bit # name description type default interface 1 5 n p n e xt page this bit is d e f a ults to 1, indica ting th at phy841f is next page capable. r/ w 0 h 1 4 r e s e r v e d r o 0 h 1 3 r f r emote fault 1 rem o te fault has been detected 0 no remote fault has been detected this bit is written by serial m a nage ment interface for the purpose of communicating the r e m o te f a ult condition to the auto negotiation link p artner. r/ w 0h s/ w should read status from register 1 (bit 1.4) and fill out this bit dur in g auto negotiation in case remote fault is d e te cted. 1 2 r e s e r v e d r o 0 h 1 1 a s m _ d i r a symmetric pause direc tion bit[11:10] capability 00 no pause 01 symm etric pause 10 asymm e tric pause toward link partner 11 both symm etric pause and asy m m e tric pause to ward local dev i ce r/ w 0h 1 0 p a u s e p ause operation for full duplex value on paurec will be sto r ed in this bit during power on reset. r/ w p i n p i _ p a u r e c 9 t 4 technology ability for 1 00base-t4 def a ults to 0. r o 0 h 8 t x _ f d x 100base-tx full duplex 1: capable of 100m full duplex operation 0: not capable of 100m full duplex operation r/ w 1h used by auto n egotiation block 7 t x _ h d x 100base-tx half duplex 1: capable of 100m operation 0: not capable of 100m operation r/ w 1h used by auto n egotiation block 6 1 0 _ f d x 10base-t full duplex 1: capable of 10m full duplex operation 0: not capable of 10m full duplex operation r/ w 1h used by auto n egotiation block 5 1 0 _ h d x 10base-t half duplex 1: capable of 10m operation 0: not capable of 10m operation r/ w 1h used by auto n egotiation block
ADM7008 register description bit # name description type default interface n ote: that bit 8:5 should be com b ined with rec100, recful pin input to determ ine th e finalized speed and duplex mode. 4 : 0 s e l e c t o r field these 5 bits are hardwired to 00001b, indicating that the phy841f supports ieee 802.3 csma/cd. ro 01h used by auto n egotiation block. 4.3.6 auto negotiation lin k partner ability (register 5h) admtek inc. 4-10 bit # name description type default interface 1 5 n p a g e n ext page 1: capable of next page function 0: not capable of next page function ro 0h updated by auto n egotiation block 1 4 a c k a cknowledge 1: link partner acknowledges reception of the ability data word 0: not acknowledged ro 0h updated by auto n egotiation block 1 3 r f r emote fault 1: rem o te fault has been detected 0: no rem o t e fault has been detected ro 0h updated by auto n egotiation block 1 2 r e s e r v e d r o 0 h 1 1 l p _ d i r l ink partner asymmetric pause d irection. ro 0h updated by auto n egotiation block 1 0 l p _ p a u l ink partner pause capability value on paurec will be sto r ed in this bit during power on reset. ro 0h updated by auto n egotiation block 9 l p _ t 4 l ink partner technology ability for 100base-t4 def a ults to 0. ro 0h updated by auto n egotiation block 8 l p _ f d x 100base-tx full duplex 1: capable of 100m full duplex operation 0: not capable of 100m full duplex operation ro 1h used by auto n egotiation block 7 l p _ h d x 100base-tx half duplex 1: capable of 100m operation ro 1h used by auto n egotiation
ADM7008 register description bit # name description type default interface 0: not capable of 100m operation block 6 l p _ f 1 0 10base-t full duplex 1: capable of 10m full duplex operation 0: not capable of 10m full duplex operation ro 1h used by auto n egotiation block 5 l p _ h 1 0 10base-t half duplex 1: capable of 10m operation 0: not capable of 10m operation ro 1h used by auto n egotiation block 4 : 0 s e l e c t o r field e ncoding definitions. ro 01h updated by auto n egotiation block. 4.3.7 auto negotiation expansion register (register 6h) bit # name description type default interface 1 5 : 5 r e s e r v e d r o 0 0 0 h 0 0 0 h 4 p f a u l t p arallel detection fault 1: fault has been detected 0: no fault detect ro, lh 0h updated by auto n egotiation block 3 l p n p a b l e link partner next page able 1: link partner is next page capable 0: link partner is not next page capable ro 0h updated by auto n egotiation block 2 n p a b l e n ext page able 0: next page disable 1: next page enable. r o 0 h 1 p g r c v p age received 1: a new page has been receiv e d 0: no new page has been receiv e d ro, lh 0 h u p d a t e d b y auto n egotiation block 0 l p a n a b l e l ink partne r auto negotiation able 1: link partner is auto negotiable 0: link partner is not auto negotiable r o 0 h u p d a t e d b y auto n egotiation block 4.3.8 register reserved (register 7h -fh) bit # name description type default interface 1 5 : 0 r e s e r v e d 4.3.9 generic p h y configuration register (register 10h) note: phy control/configuration r e gister s start from address 16 to 21. admtek inc. 4-11 bit # name description type default interfac e
ADM7008 register description bit # name description type default interfac e 1 5 : 5 r e s e r v e d r o 1 h 1 4 x o v e n cross over auto detect enable. 0: disable 1: enable r/ w p i n p i _ x o v e n 3 : 1 r e s e r v e d r o 0 h 0 d i s p m g d isable power management feature. 0: enable. enable medium detect function. 1: disable. medium _on is high all the tim e. r/ w 0 h r e c _ d i s p m g 4.3.10 phy 10m module configurat ion register (register 11h) bit # name description type default interfac e 1 5 : 6 r e s e r v e d r o 0 h 5 d r v 6 2 m a r educe 10m driver to 62ma. 1: 62ma 0: norm al r/w 0h w ill be on when disp mg is set to low during power on reset. 4 a p d i s a uto polarity disable 1: auto polarity function disabled 0: norm al r/ w 0 h r e c _ a p o l dis tp module polarity pin. 3 e n r j a b e nable receive jabber monitor. 0: disable 1: enable r/ w 1 h r e c _ e n rj a b control two blocks : 1.receive jab b er (crs keeps high all the tim e) 2.crs lo w less than 2 3 us 2 d i s t j a b d isable transmit jabber 1: disable t r ansm it jabber function 0: enable transm it jabber function r/ w 0 h r e c _ d i s t j a b 1 n t h n ormal threshold 0: lower 10base-t re ceive threshold 1: norm al 10base-t receive thres hold r/ w 0 h r e c _ n t h 0 f g d l n k f orce 10m receive goo d link 1: force good link 0: norm al operation r/ w 0 h r e c _ f gdl ink admtek inc. 4-12
ADM7008 register description 4.3.11 phy 100m module control register (register 12h) bit # name description type default interfac e 1 5 : 8 r e s e r v e d r o 0 h 7 s e l f x f iber sele ct 1: fiber mode 0: tp mode r/ w p i n ~ p i _ s e l t p 6 : 5 r e s e r v e d r/ w 1 h 4 d i s s c r d isable scramble r 1: disable s c ram b ler 0: enable scram b ler when set to fiber m ode, this bit will be f o rced to 1 a u tom a tically . w r ite 0 to this bit in fiber mode has no effect. r/ w p i n w h e n p rogramm e d to fiber m ode, set to 1 autom a tically 3 e n f e f i e nable fef i 1: enable f e fi 0: disable f e fi r/ w p i n ~ d i s f e f i ored resu lt of enfefi and ftpre n 2 r e s e r v e d r o 0 h 1 r e s e r v e d r/ w 1 h 0 r e s e r v e d r/ w 0 h 4.3.12 led configuration register (register 13h) admtek inc. 4-13 bit # name description type default interface 1 5 : 1 4 r e s e r v e d r o 0 h 1 3 : 1 2 b l i n k _ t m 10/100m blink timer select. value 10m blink tim e 100m blink tim e 00 100 ms 100 m s 01 200 ms 100 m s 10 400 ms 100 m s 11 100 ms 50 m s r o 0 0 rec_blink_t m 1 1 : 8 l n k c t r l l ink/act le d control. 0000: collis ion 0001: all errors 0010: duplex 0011: duplex/collis ion 0100: speed 0101: link 0110: transm it activity 0111: receive activity 1000: tx/rx activity 1001: link/receive activity r o 1 0 1 0 rec_lnkled_ ctrl
ADM7008 register description bit # name description type default interface admtek inc. 4-14 1010: link and tx/rx activity 1011: 100m false carrier error/10m receive jab b er 1100: 100m error end of stream /10m transm it jabber 1101: 100m sym bol error 1110: distance (see le d description for more detail) 1111: cable broken distance 7 : 4 d u p c t r l d uplex l e d control. 0000: collis ion 0001: all errors 0010: duplex 0011: duplex/collis ion 0100: speed 0101: link 0110: transm it activity 0111: receive activity 1000: tx/rx activity 1001: link/receive activity 1010: link and tx/rx activity 1011: 100m false carrier error/10m receive jab b er 1100: 100m error end of stream /10m transm it jabber 1101: 100m sym bol error 1110: distance (see le d description for more detail) 1111: cable broken distance r o 0 0 1 1 rec_dupled_ ctrl 3 : 0 s p d c t r l speed led control. 0000: collis ion 0001: all errors 0010: duplex 0011: duplex/collis ion 0100: speed 0101: link 0110: transm it activity 0111: receive activity 1000: tx/rx activity 1001: link/receive activity 1010: link and tx/rx activity 1011: 100m false carrier error/10m receive jab b er 1100: 100m error end of stream /10m r o 0 1 0 0 rec_spdled_ ctrl
ADM7008 register description bit # name description type default interface transm it jabber 1101: 100m sym bol error 1110: distance (see le d description for more detail) 1111: cable broken distance 4.3.13 interrupt e n able register (register 14h) bit # name description type default interfac e 1 5 : 1 0 r e s e r v e d r o 0 0 h 9 x o v c h g cross over mode changed interrupt e nable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 8 s p d c h g speed changed interrupt enable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 7 d u p c h g d uplex changed interrupt enable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 6 p g r c h g p age received interrupt enable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 5 l n k c h g l ink status changed interrupt enable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 4 s y m e r r symbol error interrupt e nable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 3 f c a r f alse carrier interrupt enable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 2 t j a b i n t transmit jabber interrupt enable 0: inte rrup t disable r/ w 1 h 1 r j a b i n t r eceive jab b er interrup t enable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 0 e s d e r r e rror end of stream enable 1: inte rrup t enable 0: inte rrup t disable r/ w 1 h 1: inte rrup t enable admtek inc. 4-15
ADM7008 register description 4.3.14 phy generic status register (register 16h) note: phy status registers start from 22 to 28 (29 to 30 reserves for further use) bit # name description type default interfac e 1 5 : 1 4 r e s e r v e d r o 0 0 h 1 3 c b b r k 4.3.4 phy identifier re gister (registe r 3h) 0: connection properly 1: broken r o 0 h 1 2 : 1 1 b r k d i s t [ 1:0] cable broken distance 00: 0 ? 60m 01: 60? 90m 10: 90 ? 130m 11: 130 ? 170m r o 0 h 1 0 m d m edium detect. real time status fo r medium_detect signal 0: medium _detect fail 1: medium _detect pass r o 0 h 9 f x e n f iber enable. only changed when ph y r eset 0: tx 1: fx m ode or?ed result of pi_selfx and 17.9 (selfx) r o p i n p i _ s e l f x 8 x o v e r cross over status. 0: mdi m o de 1: mdix mode r o 0 h 7 : 0 c b l e n cable length. only valid for 100m msb is ic0 8?h1c: 40 meters 8?h25: 60 meters 8?h2e: 80 meters 8?h3b: 100 m e ters 8?hbc: 120 m e ters 8?hd2: 140 m e ters r o 0 0 h admtek inc. 4-16
ADM7008 register description 4.3.15 phy specific status register (register 17h) admtek inc. 4-17 bit # name description type default interfac e 15:12 reserved ro 0h force to 0 all the tim e. 1 1 j a b - r x r eal time 10m receive jabber statu s 1: jabber 0: no jabber r o 0 h 1 0 j a b _ t x r eal time 10m transmit jabber status 1:jabber 0: no jabber ro 0h updated by 10m block 9 polar p olarity. only available in 10m 0: norm al polarity 1: polarity r e versed r o 0 h 8 p a u o u t p ause out capability. disabled when hal f duplex. 0: lack of pause out capability 1: has paus e out capability r o 0 h 7 p a u i n p ause in capability. disabled when half duplex. 0: lack of pause in capability 1: has paus e in capab ility r o 0 h 6 d u p l e x operating duplex 1: full duplex 0: half duplex r o 1 h 5 s p e e d operating s p eed 1: 100mb/s 0: 10mb/s r o 1 h 4 l i n k r eal time link status 1: link up 0: link down r o 0 h 3 r e c p a u p ause recommend value. only changed when phy reset. this bit is d i sab l e d autom a tically when recdup is 0. 0: pause disable 1: pause enable r o p i n p i _ p a u r e c 2 r e c d u p d uplex recommended value. only changed when phy res e t 1: full duplex 0: half duplex r o p i n p i _ d u p f u l 1 r e c s p d speed reco mmend value. only changed r o p i n p i _ r e c 1 0 0
ADM7008 register description bit # name description type default interfac e when phy reset 1: 100m 0: 10m 0 r e c a n e n r ecommended auto negotiation value . only changed when phy reset r o p i n p i _ r e c a n e n 4.3.16 phy recommend value status register (register 18h ) bit # name description type default interfac e 1 5 p w e d n p ower down status r o p i n 1 4 r e c a n a uto negotiation recom m end value r o p i n 1 3 s e l f x f iber select recommend value r o p i n 1 2 r e c 1 0 0 speed reco mmend value 0: 10m 1: 100m r o p i n 1 1 r e c f u l d uplex recommend value. 0: half duplex 1: full duplex r o p i n 1 0 p a u r e c p ause capability recom m end value 1: pause enable 0: pause disable r o p i n 9 d i s f e f i f ar end fault disable. 0: enable 1: disable r o p i n 8 x o v e n cross over capability r ecommend value. 0: disable 1: enable r o p i n 7 x o v e r cross over status. 0: non-cross over 1: cross over r o 0 h 6 r m i i _ s m i i r mii_smii inter f ace 1: rmii or smii in terfa ce used 0: non rmii_smii interface r o p i n 5 r e p e a t e r r epeater mode recommend value 1: repeater 0: nic/sw r o p i n 4 : 0 p h y a p hy address r o 0 h 4.3.17 interrupt s t atus register (register 19h) admtek inc. 4-18 bit # name description type default interfac e
ADM7008 register description bit # name description type default interfac e 1 5 : 1 0 r e s e r v e d cor 0 0 h 9 x o v c h g cross over mode changed 1: cross over m ode cha nged 0: cross over m ode not changed cor 0 h u p d a t e d b y pmd block 2 8 s p d c h g speed changed 1: speed changed 0: speed not changed cor 0h updated by auto n egotiation block 7 d u p c h g d uplex changed 1: duplex changed 0: duplex not changed cor 0h updated by auto n egotiation block 6 p g r c h g p age received 1: page received 0: page not received cor 0h updated by auto n egotiation block 5 l n k c h g l ink status changed 1:link status changed 0: link status not changed cor 0h updated by auto n egotiation block 4 s y m e r r symbol error 1: sym bol error 0: no sym b ol error cor 0 h u p d a t e d b y 100m block 3 f c a r f alse carrie r 1: false car r ier 0: no false carrier n ote: high whenever link is failed . cor 0 h u p d a t e d b y 100m block 2 t j a b i n t transmit jabber 1: jabber 0: no jabber cor 0h updated by 10m block 1 r j a b i n t r eceive jab b e r 1: jabber 0: no jabber cor 0h updated by 10m block 0 e s d e r r e rror end of stream 1: esd error 0: no esd error cor 0 h u p d a t e d b y 100m block 4.3.18 receive error counter register (register 1dh) bit # name description type default interfac e 1 5 : 0 e r b [ 1 5 : 0 ] e rror counter. includes r o 0 0 0 0 h 1.100m false carrier 2.100m sym b ol error 3.10m transm it jabber 4.10m receiv e jabber 5.error sta r t o f stream 6.error end of stream admtek inc. 4-19
ADM7008 register description 4.3.19 chip id re gister (register 1fh) bit(s) name r/w default interfac e 1 5 : 0 c h i p i d [ 1 5 : 0] admtek chip id ro 8818 description 4.3.20 per port interrupt and revisi on id register (register 1eh) bit # name description type default interfac e 15:8 i n t p [ 7 : 0 ] p e r p o r t i n terr upt status. only available in port 0. 1 - interrupt asserted in corresponding port 0 - interrupt not asserted in corresponding p ort r o 8 ? h 0 0 7 : 0 r e s e r v e d r o 8 ? h 0 0 admtek inc. 4-20
ADM7008 electrical specification chapter 5 electrical specification 5.1 dc characteri z a tion 5.1.1 absolute maximum rating symbol parameter rating units v cc33 3.3v power supply 3.0 to 3.6 v v cc18 1.8v power supply 1.62 to 1.98 v v in i n p u t v o l t a g e -0.3 to v cc3 3 + 0.3 v vout o u t p u t v o l t a g e -0.3 to vcc 33 + 0.3 v tstg storage temperature -55 to 155 c pd power dissipation 1.5 w esd esd rating 2000 v table 5-1 electrical absol u te ma ximum rating 5.1.2 recommen d ed operating conditions symbol parameter m i n t y p max units vcc 33 power supply 3.135 3.3 3.465 v vin input voltage 0 - vcc v tj junction operating temperature 0 25 115 c table 5-2 re commended opera t ing conditions 5.1.3 dc electrical characterist ics for 3.3v operation (under vcc=3.0v~3.6v, tj= 0 c ~ 115 c ) symbol parameter conditions m i n t y p max units vil input low voltage cmos 0.3 * vcc v vih input high voltage cmos 0.7 * vcc v vol output low voltage cmos 0.4 v voh output high voltage cmos 2.3 v ri input pull_up/down resistance vil=0v or vih = vcc 7 5 k ? admtek inc. 5-1 table 5-3 dc electrical charac teris t ic s for 3.3v o p era t ion
ADM7008 electrical specification 5.2 ac characteri z a tion 5.2.1 xi/osci (crystal/oscilla tor) timing figure 5-1 cr y s tal/oscillator timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_xi_per xi/osci clock period 40.0 - 50ppm 4 0 . 0 4 0 . 0 + 50pp m ns t_xi_hi xi/osci clock high 1 4 2 0 . 0 ns t_xi_lo xi/osci clock low 1 4 2 0 . 0 ns t_xi_rise xi/osci clock rise tim e , v il (m ax ) to v ih (m in) 4 n s t_xi_fal l xi/osci clock fall tim e , v ih (m in ) to v il (m ax) 4 n s table 5-4 cry s tal/oscilla tor timing admtek inc. 5-2 t_ x i _ r is e t_ x i _ f all v ih _ x i t _ x i _h i t _x i_lo t_ x i _ p e r v il _ x i
ADM7008 electrical specification 5.3 rmii timing 5.3.1 refclk input timing (whe n refclk_sel is set to 1) figure 5-2 refcl k input timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_in50_per refclk cl ock period 40.0 - 50ppm 4 0 . 0 4 0 . 0 + 50pp m ns t_in50_hi refclk cl ock high 1 4 2 0 . 0 ns t_in50_lo refclk cl ock low 1 4 2 0 . 0 ns t_in50_rise refclk cl ock rise tim e , v il (m ax ) to v ih (m in) 2 n s t_in50_fall refclk cl ock fall tim e , v ih (m in ) to v il (m ax) 2 n s table 5-5 re fcl k input timing admtek inc. 5-3 t _ i n 50 _r i s e t _ i n 5 0_f a l l v ih _ r mi i t _ i n 5 0_h i t _i n 5 0_l o t _ i n 5 0_p er v il _rmii
ADM7008 electrical specification 5.3.2 refclk output timing (when refclk _sel is set to 0) figure 5-3 refcl k outp ut timing s y m b o l d e s c r i p t i o n min t y p max unit t_out50_per refclk cl ock period 40.0 - 50ppm 4 0 . 0 4 0 . 0 + 50pp m ns t_out50_hi refclk cl ock high 1 4 2 0 . 0 26 ns t_out50_lo refclk cl ock low 1 4 2 0 . 0 26 ns t_out50_rise refclk cl ock rise tim e , v il (m ax ) to v ih (m in) 2 n s t_out50_fall refclk cl ock fall tim e , v ih (m in ) to v il (m ax) 2 n s t_out50_jit refclk cl ock jittering (p-p) 0 . 1 5 n s table 5-6 re fcl k outpu t timing admtek inc. 5-4 t _ o u t5 0_r i s e t_ o u t 5 0 _ f a l l v ih _ r m i i t_ out 5 0 _ hi t _ out5 0 _ lo t_out 5 0 _ p e r v il _r mii
ADM7008 electrical specification 5.3.3 rmii transmit timin g figure 5-4 rmii transmit timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_rt_dsetup txd to refclk rising setup time 2 n s t_rt_dhold txd to re fclk rising hold tim e 2 n s t_rt_txe2mh 1 00 txen asserts to da ta tra n sm it to m e dium 2 3 5 ns t_rt_txe2mh 1 0 txen asserts to da ta tra n sm it to m e dium 1 5 5 0 ns t_rt_txe2ml 10 0 txen de-asserts to f i nis h transm ittin g 2 6 0 ns t_rt_txe2ml 10 txen de-asserts to f i nis h transm ittin g 1 2 5 0 ns table 5-7 rmii transmit timing admtek inc. 5-5 re fclk tx d pr ea m tx d 0 tx d1 tx d 2 tx d 3 tx d 4 tx d 5 t_ r t _ d setu p tx e n tx d n t_ rt_ d h o l d p r eam 00 dat a on m e d i um t _ r t _t x e 2m h 00 t _ r t _t x e 2m l
ADM7008 electrical specification 5.3.4 rmii receive timing figure 5-5 rmii receiv e timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_rr_mh2 c sh 1 00 signal detected on medium to crsdv high 2 6 5 n s t_rr_mh2 c sh 1 0 signal detected on medium to crsdv high 1 0 0 0 n s t_rr_ml2csl 10 0 idle detected on medium to crsdv low 2 6 0 n s t_rr_ml2csl 10 idle detected on medium to crsdv low 5 7 0 n s t_rr_csh2 dat 100 crsdv high to receive data on rxd 160 n s t_rr_csh2 dat 10 crsdv high to receive data on rxd 1 6 0 0 n s t_rr_csl2 dat 100 crsdv toggle to end of data receiving 1 6 0 n s t_rr_csl2 dat 10 crsdv toggle to end of data receiving 1 6 0 0 n s t_rr_ddl y refcl k ri sing to rxd/crsdv de lay tim e 5 n s table 5-8 rmii receiv e timing admtek inc. 5-6 refclk t _ r r _c s l 2d a t cr s d v non_ idl e (in te r n al) t_ rr _ mh2 c s h t_ r r _ m l2 csl rxd p r eam rx d0 rx d1 rx d2 rx d4 rx d5 rx d6 rx dn p r eam 00 t _ rr _ csh2dat t_ r r _ d dl y
ADM7008 electrical specification 5.4 smii clock timing 5.4.1 refclk input timing (when refclk_sel is set to 1) - also apply to tx_clk figure 5-6 refcl k input timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_in125_per refclk/txclk clock period 8.0 - 50ppm 8 . 0 8 . 0 + 50pp m ns t_in125_hi refclk/txclk clock high 2 . 8 4 . 0 n s t_in125_lo refclk/txclk clock low 2 . 8 4 . 0 n s refclk/txclk clock rise tim e , v il (m a x ) to v ih (m in ) 2 ns t_in125_fall refclk/txclk clock fall tim e , v ih (m in ) to v il (m a x ) 2 ns t_in125_rise table 5-9 re fcl k input timing admtek inc. 5-7 t _ i n 12 5_ r i s e t _ i n 12 5_ f a ll v ih _ s m i i t_ in1 2 5 _ hi t_ in 1 2 5 _ l o t _ i n 12 5_ p e r v il _ s m i i re f c lk
ADM7008 electrical specification 5.4.2 refclk output timing (when refclk _sel is set to 1) also apply to rxclk in ss_smii mode figure 5-7 smii/ss_smii refclk ou tput timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_out125_per refclk cl ock period 8.0 - 50ppm 8 . 0 8 . 0 + 50pp m ns t_out125_hi refclk cl ock high 2 . 4 4 . 0 ns t_out125_lo refclk cl ock low 2 . 4 4 . 0 2 6 ns refclk cl ock rise tim e , v il (m ax ) to v ih (m in) 2 n s t_out125_fal l refclk cl ock fall tim e , v ih (m in ) to v il (m ax) 2 n s t_out125_jit refclk cl ock jittering (p-p) 0 . 1 5 n s t_out125_rise table 5-10 smii/ss_smii refclk ou tput timing admtek inc. 5-8 t _ o u t 1 25_ r i s e t _ o u t12 5 _ fa ll v ih _ s m i i t _ ou t1 25 _hi t _ou t 1 2 5 _ l o t _ o u t 1 25 _p e r v il _ s m i i re fclk t _ o u t 1 25_ r i s e t _ o u t12 5 _ fa ll v ih _ s m i i t _ ou t1 25 _hi t _ou t 1 2 5 _ l o t _ o u t 1 25 _p e r v il _ s m i i re fclk
ADM7008 electrical specification 5.4.3 smii/ss_smii transmit timing figure 5-8 smii/ss_smii transmit ti ming s y m b o l d e s c r i p t i o n m i n typ max unit t_st_dset u p txd to refclk rising setup time 2 n s t_st_dhold txd to re fclk rising hold tim e 2 n s t_st_txe2mh 10 0 txen asserts to data transm it to m e dium (100m) 3 9 0 ns t_st_txe2mh 10 txen asserts to data transm it to m e dium (10m) 2 3 4 0 ns t_st_txe2ml 10 0 txen de-asserts to finis h transm ittin g (100m) 4 3 0 ns t_st_txe2ml 10 txen de-asserts to f i nis h transm ittin g (10m) 3 8 0 0 ns table 5-11 smii/ss_smii transmit ti ming admtek inc. 5-9 tx c l k tx d tx er t xen = 1 tx d0 tx d1 0 t _ s t _t x e 2m h sy n c (s mii) t x _ s y n c (ss m ii) 0 t_ st _ d se t u p tx e r t xen = 1 tx er tx e n = 0 t r a n sm it t o m e d i um t_ st _ d ho l d t_ st _ t x e 2 m l
ADM7008 electrical specification 5.4.4 smii/ss_smii receiv e timing figure 5-9 smii/ss_smii rec e iv e timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_sr_mh2csh 10 0 signal detected on medium to crs high (100m) 4 3 0 ns t_sr_mh2csh 10 signal detected on medium to crs high (10m) 6 8 0 ns t_sr_ml2csl 10 0 idle detected on medium to crs l o w (100m) 4 2 0 ns 10 idle detected on medium to crs l o w (10m) 2 4 0 ns t_sr_mh2dvh 1 00 signal detected on med i um to receive data valid (100m) 4 7 0 ns t_sr_mh2dvh 1 0 signal detected on med i um to receive data valid (10m) 3 8 4 0 ns t_sr_ddl y smi i txcl k rising to sync/rxd delay tim e (smii) 5 ns t_sr_ddl y ss_s mii rxcl k ris i ng to rx_sync/r xd delay tim e (ss_smii) 5 ns t_sr_ml2csl table 5-12 smii/ss_smii rec e iv e timing admtek inc. 5-10 t x c l k (smi i) rx cl k ( ss_ s m i i ) rxd cr s = 1 rx dv = 0 rx d6 fce t_ sr_ d d l y s ync (smi i) rx_sync ( ss_smi i ) rx d7 rx d7 crs = 0 rxdv = 0 non_i d l e (internal) cr s = 1 rx dv = 1 t_ s r _ m h 2 csh t_ sr_ m h2 dv h rx d5 va l i d t_ s r _ m l 2 csl
ADM7008 electrical specification 5.5 serial management interface (mdc/mdio) timing figure 5-10 serial mana gement inter f ac e (m dc/m d io) timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_mdc_per mdc period 1 0 0 ns t_mdc_hi mdc high 4 0 ns t_mdc_lo mdc high 4 0 ns t_mdio_dly mdc to mdio delay tim e 2 0 ns t_mdio_setup mdio input to mdc setup tim e 1 0 ns t_mdio_hold mdio input to mdc hold tim e 1 0 ns table 5-13 serial manage ment inter f a ce (m dc/m d i o ) timing admtek inc. 5-11 md c mdio( o u tpu t) t_ md i o _ d l y md c m d i o ( i np ut ) t _ m d i o _s etu p t_ md i o _ hol d t_ md c_ l o t_ md c_ p e r t_ mdc _ hi
ADM7008 electrical specification 5.6 pow e r on configuration timing figure 5-11 po w e r on configura t ion timing s y m b o l d e s c r i p t i o n m i n t y p max unit t_v33_v18 3.3v power good to 1.8v power good t b d ms t_v18_rst hardware reset w ith device powered up 2 0 0 ms t_rst_pw hardware reset w ith clock running 8 0 0 ns t_pl_dset u p reset high to configuration setup tim e 2 0 0 ns t_pl_dhold reset high to configuration hold tim e 0 ns table 5-14 po w e r on co nfigura t ion t i ming admtek inc. 5-12 vcc3 . 3 rst _ n t _ v 18_ r s t re fcl k t_r s t _ pw t_ p l _ d ho l d t_p l _dset u p pw r o n lat c h vcc1 . 8 t _ v 33_ v 1 8
model: xx appendix chapter 6 packaging admtek inc. 6-1 18.5 mm 20.0 +/- 0.1 mm 23.2 +/- 0.2 mm 3.4 mm max 12.5 mm 14.0 +/- 0.1 mm 17.2 +/- 0.2 mm 0.5 mm

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